What's the difference between Logic Synthesis and Physical Synthesis?

[cooldude040]

Difference between Logic Synthesis and Physical Synthesis?

 

[asicganesh]

Synthesis question

Of course, there is a difference between logic synthesis and physical synthesis. Typically, the former maps an RTL description to a set of gates to realize the same functionality. Conversely, the latter implements the netlist on a given (minimal) floorplan and maintains or improves the quality of physical characteristics of the design. These characteristics could include timing, power, testability, signal integrity, routability and manufacturability, all leading to improved yield for the device.

Looking through the reality viewfinder, however, shows a much different perspective for many design project teams. For example, logic synthesis is a disparate step, performed in almost complete isolation. The logic design engineer writes (or receives) functionally verified RTL code and begins to synthesize it with incomplete timing constraints. Whether the concept of wireload is used for selecting the most optimal cells, traditional methods ignore a design’s physical requirements. This leads to a false sense of "timing closure" too early in the design process and a false sense of confidence that the logical netlist can be implemented by the physical design team.

Better have a look at this article
https://www.soccentral.com/results.asp?CatID=488&EntryID=16959

 

[dmk]

Re: Synthesis question

Have a look.
RTL is the result after Logic synthesis.
Tech1, 2, 3, 4, 5 - the same circuit after physical synthesis (in selected technology).
I think, the difference is clear now.