what's the difference betw. SRAM & register file?

[hgby2209]

sram based register architecture

I use foundry's memory compiler to generate SRAM & Register file. And find regidter file 's power consumption, access time, and area are better than SRAM, so I want to use register file to replace SRAM, but I don't know what's the difference between them? RAM Cell structure different or decoder circuit different?

 

[tarkyss]

rf sram area memory compiler

register file is a architecture term
it can be implemented with SRAM

 

[wadaye]

difference in register file and sram

Hi hgby2209,

You can use memory compiler generate RAM or Register File. The difference is you

can use generate lager capacitance(bytes) RAM than Register File.

 

[hgby2209]

difference sram register file

I want to know what Architecture difference between them.

 

[BigDogBear]

memory compiler for small signal arrays

Did the SRAM and Register File you have compared have the same size(i.e, the same cell quantity)? In the compiler help documents, is there any remark on this issue when the compiler generates the SRAM and Register File? Maybe you can get the answer from them.

 

[tarkyss]

difference between sram cell and register file

in my opinion,my mean is the two term are in two different level,
register files is from computer architecture, while SRAM are from physical struture,
register file normally is small, and can be implemented with SRAM,
SRAM can be used as register file, and larger memory too.
so I think it is of no use to compare the two

 

[blanket]

difference between ram and register-file memories

Wow...I don't see anyone answering to the point.

As far as my knowledge goes, Register File is a large signal array.
SRAM on the other hand is a small signal array.

What this means is SRAM designs use bit line differential signalling and hence generally faster than register files.

Please correct me if I am wrong.

 

[hgby2209]

register file and sram

Here are two bolck diagram from Ram compiler. I can't find out the difference between them except "OEN".

 

[silencer3]

register sram cell

Register file is used when the depth of memory is less and width is more.

SRAM is used when high depth memory is needed.

But SRAM is faster, but requires MBIST in asic. Where as register file is slower and less dense and it does not require MBIST in asic, it is tested using scan chain.

Correct my comment if i am wrong.

 

[hgby2209]

difference between register file and sram

I asked Artisan and their answer is:

" There is no difference in the basic architecture, but the Register File is optimized for
better performance with smaller instance sizes. "

 

[bg21359]

register file sram difference

In CPU related fields, register file is usually used for faster access to memory, multiport operation(such as read & write at the same time, or read out the memory content in multiple ports) which requires much smaller memory capacity(KB) and much larger memory cell size(um*um) comparing with cache(L1 and L2).

 

[AlexWan]

artisan ram oen

A register file is an array of processor registers in a central processing unit (CPU).

Modern IC-based register files are usually implemented by way of fast static RAMs with multiple ports. Such RAMs are distinguished by having dedicated read and write ports, whereas ordinary multiported SRAMs will usually read and write through the same ports.

 

[incisive]

sram and register file

SRAMS are handcrafted using the 6t transistor technology and the registers are what we say flip flops or latches storing elements. SRAMS are less in Area compared to Registers.

Thanks
Incisive

 

[atul799]

sram or register array

regsiter files are not necessarily composed of flip flops.in general RFs are basic Sram cell with more than one port (separate read write port or more than one read write port ) there are different prefferred implementations in one basic sram cell is used(RF compilers) and in other read and write ports are separated.
RFs should be used when the parallelism (word length) is high and high speed is required. area some times is bigger than sram cell

 

[linglijun]

+register file +sram

Here are two bolck diagram from Ram compiler. I can't find out the difference between them except "OEN".

I also have the two bolck diagram at hand.but i want to make a comparision on them at the circuit level now,have u ever did some study on them .could you give me some useful reference information including your opinion or your research results or some useful documents,urgently for your help.thanks
you'd better give me email,and my email address is linglijun911@163.com
Regards
linglijun

 

[lever]

sram vs register file

Does it mean that register file is the optimization from SRAM?
And if I want to use 1kbit FIFO, which type of the memory array is better ?

I asked Artisan and their answer is:

" There is no difference in the basic architecture, but the Register File is optimized for
better performance with smaller instance sizes. "

 

[naveenkrishnan]

register file sram artisan difference

Here is some info on this:

http://www.vlsiforum.com/index.php?topic=12.0

 

[sunjimmy]

flops register file sram

Hi,
Usually registered file should be operated as fast as possible with acess time within 1 CLK cycle like the CPU core speed. So it can be implemented as either SRAM architecture or array of DFF architecture. The decidion factor is access time.

If SRAM architecture is used to implement register file. To enhance the speed, the SRAM cells per column must be minimized to reduce the bit-line cap per column, so the area efficiency is sacrified to gain speed. That's the reason why register file is usually smaller.

But for current advance technology like 0.18um, 200~400MHz SRAM speed is easy to achieve. So SRAM-type registered file is good enough. But for 1GHz or higher speed registered file, SRAM-type architecture can't achieve this speed. Usually fully-customed registered file is used.

Hope it helps

 

[arindrajiitkgp]

Hi Hgby2209,

I have seen your thread. But i didn't able to see any right ans from this forum. No one highlighting the basic differences. Before giving ans, i want to ask you few question:

1. You already compared two desgin (a) SRAM based (b) RF based memory. Tell me bit-cell wise difference between the two architecture?
2. Send me the area, power and performance analysis number, and tell me how are you geting better in RF based design?

Now coming to the point ans:

a. Bit Cell Wise difference:

RF Bitcell: 8 transistors. it is 1R1W cell. here read and write ports are different, so no read wright conflict. Compare to SRAM bit-cell it's area is more.
SRAM bit-cell: 6 transistors. it is 1RW cell. here same word line and bit-lines are used for both read and write operation.

b. Architecture wise difference:

RF Architecture: as read and write ports are different, so separate decoder logic is required for read and write operation. That means decoder area will be twice comapare to SRAM decoder. Other thn that architecture, and floor plan wise lot of differences are there.

SRAM Architecture: we can do either read or write at a time, so same decoder logic is used for both read and write operation. other than that sense amplifier is required.

c. Area Analysis:

compare to RF, SRAM area will be smaller because of above two major reason, for a same size memory.

d. performance:

compare to SRAM, RFs performance will be better, because read and write ports are separated.

let me know, if you want anything further details...

thanks

 

[ee171]

What you compared are not equal. How about this:
single-port SRAM VS 1-port RF
dual-port SRAM VS 2-port RF

These are the options you have from ARM if you download them. Someone earlier mentioned about the minimum size of SRAM. Artisan can't make really really small SRAM but they can make 1-port RF.