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what's the diff between Pre_layout and Post cell delay cal

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bendrift

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delay calculations

what's the diffirence between pre_layout and post_layout in cell delay calculation?
in the library , cell delay is affected by the input transition and output capacitance.
but during pre_layout ,the RC on the wire is not exact.is it will affect the gate delay calculation?
and many times , i saw the delay calculation refer to capacitance, but where the resistance reveal in library and in the cell delay calculation?
thank u :)
 

iamchine

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Re: what's the diff between Pre_layout and Post cell delay c

In general pre-layout use EWL(estimate wire load model) to calculate network delay.
 

nittinsharma80

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Re: what's the diff between Pre_layout and Post cell delay c

Hi,
Read the attached pdf.
I assure you this will remove all your doubts regarding the cell delay calculations and will further add to your knowledge.
do let me know if i am wrong in saying this.
regards
 

    bendrift

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bendrift

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thank for ur help,nittinsharma80!
it's a very good paper for sta.
do u have deep material for postlayout sta?
for i am not familiar with SPEF and Arnoldi.
best regards
:)
 

silencer3

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i suggest u use report_delay_calculation option in pt. This gives complete info on how it computes delays.

or one can use report_timing with justify option.
 

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