yagi
Newbie level 4
Hello all,
I am designing a 10b 150Msamples/sec with input bandwidth of 200Mhz. I was going through the IEEE publications and found the following paper
"10b 200Msps CMOS parallel pipeline ADC" L.sumanen, halonen.
There is a technique called "double sampling pipeline ADC" in which the ota is used in both clock phases to produce the residue.
I have designed earlier a 10b pipeline ADC arechitectures that could sample the input at 100Mhz, so if I use the same ota now in doubling sampling architecure the effective sampling rate will now be 200Msamples/sec.
I am not sure what could be the possible disadvantages with above approach to obtain 200Msamples/sec sampling frequency other than power dissipation compared to the Halonen's ADC refered above.
Please let me know what is the best architecure to use if I am looking for " 10b 150Msamples/sec with input bandwidth of 200Mhz".
Thanks,
Yagi
I am designing a 10b 150Msamples/sec with input bandwidth of 200Mhz. I was going through the IEEE publications and found the following paper
"10b 200Msps CMOS parallel pipeline ADC" L.sumanen, halonen.
There is a technique called "double sampling pipeline ADC" in which the ota is used in both clock phases to produce the residue.
I have designed earlier a 10b pipeline ADC arechitectures that could sample the input at 100Mhz, so if I use the same ota now in doubling sampling architecure the effective sampling rate will now be 200Msamples/sec.
I am not sure what could be the possible disadvantages with above approach to obtain 200Msamples/sec sampling frequency other than power dissipation compared to the Halonen's ADC refered above.
Please let me know what is the best architecure to use if I am looking for " 10b 150Msamples/sec with input bandwidth of 200Mhz".
Thanks,
Yagi