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What's the best architecture for a high speed ADC?

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yagi

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Hello all,

I am designing a 10b 150Msamples/sec with input bandwidth of 200Mhz. I was going through the IEEE publications and found the following paper
"10b 200Msps CMOS parallel pipeline ADC" L.sumanen, halonen.

There is a technique called "double sampling pipeline ADC" in which the ota is used in both clock phases to produce the residue.

I have designed earlier a 10b pipeline ADC arechitectures that could sample the input at 100Mhz, so if I use the same ota now in doubling sampling architecure the effective sampling rate will now be 200Msamples/sec.

I am not sure what could be the possible disadvantages with above approach to obtain 200Msamples/sec sampling frequency other than power dissipation compared to the Halonen's ADC refered above.

Please let me know what is the best architecure to use if I am looking for " 10b 150Msamples/sec with input bandwidth of 200Mhz".

Thanks,
Yagi
 

high speed ADC

The first method is better.
 

Re: high speed ADC

Hello Sunking,
Do you mean using a parallel pipelined ADC architecure is a better approach.
If yes:

I also want know what could be the possible issues with double sampling technique if we would like to design at 150 or 200Mhz sampling frequency. I appreciate any references that talk about these issues.

Thanks
Yagi
 

high speed ADC

expecting
I am thinking of the same question like yaqi

regards
 

Re: high speed ADC

Hey, I am a bit confused with the original question, which says, a sampling rate of 150MSPS where the analog input BW is 250MHz, if I have understood correctly. I dont know how analog BW could be greater than the sampling rate.

Any way, there are several methods for achieving the target. It will also depend on the technology u r using. It it is same or below 0.35um CMOS you could go for simple pipelined 1.5bit/2.5bit per stage architecture. This one is popular. If the technology cannot meet the same, you may have to go for a high speed architectures (may be Folding interpolating). But again you have a requirement of 10 bit resolution. If your analog input is 1Vpp, the the resolution is approx. 1mV which is very tough, particularly for the S/H. So you may have to find some architectures those potentially does not demand S/H (like Folding Interpolating - FI). But I think FI cannot give 10bit resolution with good reliability. You may go through the following refernces for trouble shooting purpose.

1. Jun-05, JSSC, "A 16-bit...", Alfio Zanchi -- > for the whole system: this one is of SiGe technology, but can give some concepts
2. May-05, JSSC --> few papers


On the double sampling:
As far I know this requires a non-overlaping clock and is one of the bottlenec.
 

Re: high speed ADC

Hello Sankudey,

Many thanks for the reply. I am little confused on your statement about double sampling. How can non-overlapping clock be the limitation.

Case 1:
For 100Msps ADC without double sampling,
clock period Tclk = 10ns; Tclk/2= 5ns;

I can have 0.8ns of nonoverlap period hence effectively I have 4.2ns for the OTA to settle.

Case 2:
Lets consider the 200Msps ADC with double sampling,

Tclk = 5ns ; As the ota is used in both phases, I can still have 0.8ns as nonoverlap period and 4.2ns of settling time for the OTA.

Hence with the same OTA that we have used in Case1 and with parallel capacitor structures around ota, we can use the OTA in both phases to produce residue.

What could be possible problems with the above approach in Case 2 to obtain 200Msps of sampling speed with 100Msps OTA

Thanks
Yagi
 

high speed ADC

to yagi
for case 2
Doudle sampling tech usually applied in filters,ΔΣ modulators and pipelined ADCs without speed up the OTA. But OTA'srecovering time may affect doubling the sampling speed. While double sampling need more switches, which can produce more distortion in T/H.

following papers may help u

[1] T. C. Choi, R. W. Brodersen, Considerations for High-Frequency
Switched-Capacitor Ladder Filters, IEEE Trans. Circuits and Systems, vol.
cas-27, pp. 545552, Jun 1980.
[2] D. Senderowicz, G. Nicollini, S. Pernici, A. Nagari, P. Confalonieri, C.
Dallavalle, Low-Voltage Double-Sampled  Converters, IEEE J. Solid-
State Circuits, vol. 32, pp. 19071909, Dec. 1997.
[3] S. Bazarjani, M. Snelgrove, A 40 MHz Double-Sampled SC Bandpass 
Modulator, in Proc. IEEE International Symposium on Circuits and Sys-
tems, 1997, pp. 7376.
[4] W. Bright, 8b 75MSample/s 70mWParallel Pipelined ADC Incorporating
Double Sampling, in 1998 IEEE International Solid-State Circuits Confer-
ence, Dig. Tech. Pap., pp. 146147, 1998.


and for ur case 1, the overlap period of clock is much less than 0.8ns, and 4.2ns is enough for OTA to settle when 1V-Vpp and 100Mhz speed.

Added after 15 minutes:

To yaqi

I noticed that you read the paper
"10b 200Msps CMOS parallel pipeline ADC"
and got confused by double sampling.
while i think T/H 's OTA does not operate in 100Mhz. The paper represents a paralled pipelined ADC, so it has at least 2 slice of pipelined ADC, which means each slice operate at 100Mhz. As a result, Double sampling T/H has doubled loads. That challenge the design a lot.

regards
 

Re: high speed ADC

Hi wsy979,

Thanks a lot for the explicit reply. I took long time to read those papers. I could understand the possible problems to careful about during design. But I could not understand to what speed and resolution do they limit the peformance of the ADC. So still could not come to a conclusion on what is the architecture that best suits my specifications.

"10b 150MSPS Analog bandwidth= 200Mhz, Imax = 120mA".

What could be the best choice from the following:

1. Double Sampling architecture.
2. Parallel pipeline ADC with 2 time interleaved pipelined ADCs
3. Standard 1.5b/stage Pipeline ADC.
4. Any other.

References on very high speed and high resolution ADC will be of great help to me.

Also I have a question on your following statement:

"To yaqi

I noticed that you read the paper
"10b 200Msps CMOS parallel pipeline ADC"
and got confused by double sampling.
while i think T/H 's OTA does not operate in 100Mhz. The paper represents a paralled pipelined ADC, so it has at least 2 slice of pipelined ADC, which means each slice operate at 100Mhz. As a result, Double sampling T/H has doubled loads. That challenge the design a lot.
"

In the paper he used a 4 parallel double sampling pipeline ADC, but Double sampling T/H will be loaded with only one ADC at any time. I understand there will be too many clocks which would increase the complexity.


Thanks for sharing valuable information,
Yagi
 

high speed ADC

Dear Yaqi
what I said is different with the paper of Bright, he used one s/h for each slice, but I was thinking about only one s/h for the adc driving all the slice.
 

Re: high speed ADC

Hi Yagi,
I don't know whether you have gone through the references for higher resolution ADCs. I have very few points to add to the above discussions...

1. Have you checked whether ur technology could meet the requirement of 200MSPS even without employing double sampling.....I know some of my friend doing 1.5b per stage pipelined ADC for 200 MSPS ...they go by simple pipelined architecture....but their technology is 0.25um...for ur case 0.35um.....

==> the thing is that if you could mee all the other spec for the ADC (like resolution and hence DNL/INL/SNR/SFDR etc. etc.) at say x-samples/second, then by double sampling you probably could acieve the same spec(may be a little degraded) at 2x-samples/second by putting two ADCs in parallel and going for time-interleaved......may be, u could predict the above for ur tech. withou doing the full task but some blocks u already have designed and some more calculations.......


There are several factors those determines the architectures to be folloed....In my opinion, you may need to go for pipelined (1.5bit or 3 bit etc. per satge) and don't the interleaved... may be the T/H requires the double sampling....again, I have not worked with non-overlaping clocks...thus cannot specify much problems of the same....

All the best,
sankudey
 

Re: high speed ADC

I have already studied some double sampling techniques, and implemented a chip

for 10-bit 200MS/s pipelined ADC for my master degree. First of all, double

sampling (parallel) pipelined adc is a little different from the time-interleaved ones.

For time-interleaved type, it requires more channels to increase the total sampling

rate, and actually the area and power will be consumed more and more. However,

the double sampling technique can not only used in S/H but also in MDAC of each

stage with the ota shared with two channels. only switches and caps need to be

increased. But timing skew will degrade the SFDR and SNDR.
 

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