What's Nonpipelined bus mean?

[davyzhu]

Hi all,

I always heard Nonpipelined bus. Is any bus Nonpipelined? Or is there Pipelined bus or other types of bus. Thanks in advance!

Best regards,
Davy

 

[IanP]

• Read Nonpipelined (synchronous—one clock
edge): In the standard read mode, new data is
driven onto the RD bus in the same clock cycle
following RA and REN valid. The read address is
registered on the read port clock active edge and
data appears at RD after the RAM access time.
Setting PIPE to OFF enables this mode.


• Read Pipelined (synchronous—two clock edges):
The pipelined mode incurs an additional clock
delay from the address to the data but enables
operation at a much higher frequency. The read
address is registered on the read port active clock
edge, and the read data is registered and appears
at RD after the second read clock edge. Setting
the PIPE to ON enables this mode.

Regards,
IanP

 

[davyzhu]

Hi all,

I have got the result from comp.lang.verilog.

//-----------------
For non-pipelined bus, all master requests interleave with slave
responses:
Req - Resp - Req - Resp .....

In pipelined bus, master may send 1<=N<=PD requests in sequence, while
receiving responses later:
Req1 - Req2 - Req3 - Req4 - Resp1 - Resp2 - Resp3 - Resp4 ....


PD is a pipeline depth of the bus.
//---------------------

Best regards,
Davy