what's challenge for 90nm semi-constom digital design?

[xworld2008]

what are the challenge for 90nm semi-constom digital design?
what are the better flow?

 

[arunragavan]

dude.. excellent :d

currently there was the .13 and .18 micron technology. in .18 micron they used aluminium and .13 they used copper.. for the .09 or 90nm tech. wiring is the main problem. They are finding a better wiring solution. GaAs seem to be a better solution. currently in 90nm technology wiring delay is more than the total chip delay i.e gate delay.

Here 75% of the total delay in the chip is due to wiring.

SoC encounter can be used to evaulate micron.. here next generation is nano encounter ie first encounter. basically 10million gate count nano meter design and floor planning is flat.

the main problem is also the signal integrity, which always a major concern.

problems such as reflection, de couplin capacitances, electromagentic inteference,cross talk and bypass capps are major problems..

hope this helps you..

with regards,

 

[power-twq]

The chanllege in 90 nm is:

crosstalk;

power;

productivity;

timing closure;

what are the challenge for 90nm semi-constom digital design?
what are the better flow?