what's "a Tiehi and Tielo gate" ?

[mic_huhu]

tiehi

what is a Tiehi and Tielo gate ?

thks

 

[semiconductorman]

tielo

Tiehi -> Tie - Hi ... used to tie off a net to High and other way around for tielo

 

[yasonwang]

cmos tiehi cell

TieHI/LO usually is one ESD protection diode preventing input poly oxide stroken by electro-static current.

 

[spauls]

tiehi tielo

tie 1 and tie 0 gate are used to get rid of 1'b0 and 1'b1 statements in netlist .
Because back end tools wouldn't understand 1'b0 and 1'b1.

 

[linuxluo]

tiehi cell

hi,
1. connect the signal 0 1 to gnd and vdd but not for gate gnd/vdd pins
2. provide esd protection

 

[jackson_peng]

tiehi cell circuit

a signal can't be direct connect to VDD bacause the start vdd may be too high to destory the cell.
so, a TIEHI cell is needed.

it contians of a PMOS with its gate connect to VDD through a active DIODE, inorder to provide a dynamic resistence.

the TIELO is likewise

 

[lionchen]

tielo cell

using TIEHI, TIELO cell, which builds in ESD protections, to protect the gate the input of connected cells. But it incurs more buffers and routing for constant, and may confuse the ERC , but using them is a protection to ur circuit, if u dont have other methods.

 

[haosg]

tiehi cells

tihi will output a 1'b1( hige level), instead of connecting VSS to standard cell's input.
tilo will output 1'b0.

 

[power-twq]

tiehi esd

essentially, they are pullup and pulldown resister,

if we cant to tie chip's internal node to high or to low,

we can use them. because if we tie internal node direct to

power or gnd, there is ESD shock risk to internal circuit.

so tiehi and tielo can provide some ESD protection.

what is a Tiehi and Tielo gate ?

thks