Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what will happen if we dont use filler cells?

Status
Not open for further replies.

coolrak

Member level 4
Member level 4
Joined
Aug 16, 2005
Messages
73
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,989
Hi Everybody,.

I understand that we need filler cells to fill the gaps in standard cells.But I want to

know what will happen if there are gaps in standard cells.

Thanks in advance
 

Nandy

Advanced Member level 4
Full Member level 1
Joined
Dec 16, 2005
Messages
116
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,298
Location
San Jose CA
Activity points
2,399
It doesn't matter if there is gap, but it's a waste to leave the space open. The filler cells can be used as ECO spare cells. When chip is back with some bugs, you can use these cells to do metal ECO.
In case you do any ECO, you can try the GUI netlist ECO tool, GOF, which can do functional/metal ECO. Check the link out
https://www.nandigits.com/metal_only_eco.htm
 

coolrak

Member level 4
Member level 4
Joined
Aug 16, 2005
Messages
73
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,989
Hi Nandy thanks for the information. But inserting filler cells is negatively affecting my

timing. I want to know the negative affects if we dont put filler cells.

Thanks in advance
 

Nandy

Advanced Member level 4
Full Member level 1
Joined
Dec 16, 2005
Messages
116
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,298
Location
San Jose CA
Activity points
2,399
You are not supposed to move the normal cells when inserting the filler cells.
Only when timing is clean, you can do the insertion.
You would have difficult to do metal ECO if there is no spare cells (filler cells)
 

greensand

Newbie level 4
Newbie level 4
Joined
Aug 21, 2004
Messages
7
Helped
0
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
60
I think inserting fill cells is for mechanical concern.
 

semi_jl

Member level 4
Member level 4
Joined
Feb 24, 2006
Messages
78
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,813
I also think inserting filler cells is for metal ECO, as description of Nandy, but greensand's hears with reason, too.
 

jcchan

Member level 1
Member level 1
Joined
Apr 28, 2005
Messages
33
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
1,569
The filler cell is used to connect well and power line of standard cell and to do this is good for yield.
 

pra

Member level 5
Member level 5
Joined
Jan 8, 2005
Messages
85
Helped
6
Reputation
12
Reaction score
2
Trophy points
1,288
Activity points
672
hi jcchan,
jcchan said:
The filler cell is used to connect well and power line of standard cell and to do this is good for yield.

could u plz explain this?
i m not sure how this effects the yeid?
 

leeenghan

Advanced Member level 4
Full Member level 1
Joined
Dec 28, 2004
Messages
118
Helped
16
Reputation
32
Reaction score
8
Trophy points
1,298
Activity points
1,333
Hi Guys,

Filler cells is not related to yield, mechancial stress etc. It is also not to connect power rail.

The main reason for filler celll is not to have DRC. For example, every standard cell has a nwell. If two standard cells are place side by side with a gap (the smallest gap is called the placment grid. It is larger than the manufacturing grid. Maybe it is M2 pitch, I am not sure...), then there will be a nwell-to-nwell DRC violation. By closing the gap with the filler cell, than it the nwell in the filler cell will abut the nwells into one nwell.

Since we need filler cell, additional function has been added to the filler cell, like well/substrate tap, transistor array, decoupling caps etc.



Regards,
Eng Han
www.eda-utilities.com
 

semi_jl

Member level 4
Member level 4
Joined
Feb 24, 2006
Messages
78
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,813
Hello leenghan, your's speaking is very clear, but could you sure that the filler cell is only for DRC check?
 

coolrak

Member level 4
Member level 4
Joined
Aug 16, 2005
Messages
73
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,989
hi leeenghan,
Thanks for the information.You explanation is very good.
 

leeenghan

Advanced Member level 4
Full Member level 1
Joined
Dec 28, 2004
Messages
118
Helped
16
Reputation
32
Reaction score
8
Trophy points
1,298
Activity points
1,333
Hi semi_jl,

The main reason is not to have DRC, but it is not the only use. To summaries, if you don't put filler cell, than you will have DRC error.



Regards,
Eng Han
www.eda-utilities.com
 

funster

Full Member level 4
Full Member level 4
Joined
Jun 30, 2005
Messages
232
Helped
19
Reputation
38
Reaction score
4
Trophy points
1,298
Activity points
2,742
There is a CMP process in chip fabrication process,

it require some amount of metal density to ensure

CMP's uniformity, so we need filler cells to fill

the gaps.

best regards




coolrak said:
Hi Everybody,.

I understand that we need filler cells to fill the gaps in standard cells.But I want to

know what will happen if there are gaps in standard cells.

Thanks in advance
 

r_p_sanna

Member level 3
Member level 3
Joined
Oct 18, 2004
Messages
65
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
569
Can we assume that if std.cells are placed in different rows, its possible to use filler cell as feedthrough to connect them using vertical routing ?
 

leeenghan

Advanced Member level 4
Full Member level 1
Joined
Dec 28, 2004
Messages
118
Helped
16
Reputation
32
Reaction score
8
Trophy points
1,298
Activity points
1,333
Hi r_p_sanna,

You can do this, but you shouldn't. Use placement blockage to do this.

If there is no metal geometries in the filler except at the power rail, then filler cells should be inserted after detailed routing or just before tape-out for full DRC/LVS check. If not, it can be insert after CTS (just before detailed routing).

Regards,
Eng Han
 

semi_jl

Member level 4
Member level 4
Joined
Feb 24, 2006
Messages
78
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,286
Activity points
1,813
Hi, leeenghan, I think I should agree with you.
 

r_p_sanna

Member level 3
Member level 3
Joined
Oct 18, 2004
Messages
65
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
569
Hi,
thanks for the info. Read about feedthroughs in ASIC book, but wasn't sure about using it in filler cells.
 

pra

Member level 5
Member level 5
Joined
Jan 8, 2005
Messages
85
Helped
6
Reputation
12
Reaction score
2
Trophy points
1,288
Activity points
672
Hi,

Thanks Leenghan and Funster for ur valuable inputs.
Does anybody have some reference to get more idea and how it can be done??

Thanks
 

prahullchintu

Newbie level 6
Newbie level 6
Joined
Dec 28, 2012
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,351
what are the DRC violations we are getting placing nwells of two standard cells side by side?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top