What will happen if we add more vias in layout?

[surianova]

hi all!

if i connect 2 metal with a lot of Via, it will cause the parasitic of capacitance to inrease or reduce? as i know, it will reduce the resistance.

 

[hmsheng]

via in layout

More via will cause large parasitic capacitance, while less parasitic resistance and inductance.

 

[DZC]

via in layout

What parasitic did U afraid of?
What's the matter with two metals conduct the same signal?

 

[sridhar540]

Re: via in layout

THIS IS SRIDHAR


USING LARGER NO OF VIAS REDUCES THE RESISTANCE FOR SURE BUT BY USING MORE NO OF VIAS THE PARASITIC CAPACITANCE INCREASES WITH THE ADJACENT NETS.
SO DEPENDING ON UR IMPORTANCE U CAN CHOOSE ANYTHING.
U CAN TRY THESE BY EXTRACTING THE LAYOUT AND SEEING THE PARASITICS.

 

[mariam_TELNET]

Re: via in layout

Hi,

The number of Via within two metal reports your circuit more strength.


Good Work.

 

[dabing]

via in layout

If the two metal are connected together, there are no parasitc captance.
there should be dieletric between the capitance

 

[wgchan_do]

Re: via in layout

Agree with SRIDHAR. More vias more capacitance.

 

[yaasi]

via in layout

adding more vias will reduce the resistance but in turn will increase the capacitance

 

[jecyhale]

Re: via in layout

Parasitic capacitor is detemined by the area of the metal.

In my opinion, I don't think it will be larger with more vias.

 

[Fom]

via in layout

Capacitance between what?

 

[jecyhale]

Re: via in layout

Capacitance between what?

There are much parasitic, for example between this metal with GND, VDD or other metal.
But I think they don't change obviously.

 

[layoutmaster]

via in layout

This is totally nosense...

The reduced resistance is not parasitic... is the CONTACT resistance what is drastically reduced when you increase teh qty of VIAS... now, if the capacitance (parasitic) increases (thing I'm not that sure) and will affect you in some way let me say you WERE DEAD a long time before...

 

[forkschgrad]

Re: via in layout

lot's of via the higher the reliability but the higher the cost.

 

[mvreddy]

Re: via in layout

More vias gives reliability along with less parasitic resistance but with the expense of higher parasitic capacitance

 

[aziznokia]

Re: via in layout

More via is better to prevent issues such electromigration and Idrop.

 

[gksivas]

Re: via in layout

i think resistance will reduce and capacitance will increase, but i dont know where the capacitance will increase.

 

[quaternion]

Re: via in layout

I think if one of the parasitic capacitance contributers is the vias effective (lateral or cross-section or..) area .So The vias distribution will have a role as well.