What will happen if I declare wire and port with same name in verilog

[mail4idle2]

What will happen if I declare wire and port with same name in verilog ?
Please refer to below example for question (clk1 is declared as port and wire )

module test (
clk1,
rstn1,
out1 );

input clk1;
input rstn1;
output out1;

wire clk1;

counter U0_counter (
.clk1 (clk1),
.rstn1 (rstn1),
.out1 (out1) );

endmodule




module counter (
clk1,
rstn1,
out1
);

input clk1;
input rstn1;
output out1;

reg [4:0] counter;

always @ (posedge clk1 or negedge rstn1)
begin
if(~rstn1)
begin
counter <= 5'd30;
end
else
begin
if (counter == 5'd0)
begin
counter <= 5'd30;
end
else
begin
counter <= counter - 2'd2;
end

end
end

assign out1 = counter[0];

endmodule

 

[dave_59]

Verilog implicitly connects a port to a signal with the same name. If you don't declare the signal, Verilog implicitly creates a wire for you with the same name as the port, as is the case with rstn1 and out1.

I highly recommend using the Verilog-2001 way of declaring ports and signals together so that each name only appears once.

module test (
 input wire clk1,
 input rstn1,
 output out1
);

 counter U0_counter (
                           .clk1 (clk1),
                           .rstn1 (rstn1),
                           .out1 (out1) );
endmodule

wire is still the default kind of signal, so it is not needed here, or you can put wire on the other ports to make everything explicit.