What type of digital circuits, VHDL

[mr_l]

Hello!
I need some help with following code.
What types of digital circuits, are these:
I guess it's some type of encoder in the first case and counter in the second one. I try to find more information on the web but I can't.
Any information or clue is welcome.

1. architecture rtl of D2a is
begin
process (X0, X1, X2)
begin
case (X0 & X1 & X2) is
when "100" => z <= '1';
when "010" => z <= '1';
when "001" => z <= '1';
when "101" => z <= '1';
when others => z <= '0';
end case;
end process;
end D2a;

2.entity asc is
generic (CS : integer := 8)
port (k, ars, srs, e, u: in std_logic;
r: buffer std_logic_vector(Cs-1 downto 0));
end asc;
architecture arch of asc is
begin
p1: process (ars, k) begin
if ars = ‘1’ then
r <= (others => ‘0’);
elsif (k’event and k=’1’) then
if srs=’1’ then
r <= (others) => ‘0’);
elsif (e = ‘1’ and u = ‘1’) then
r <= r + 1;
elsif (e = ‘1’ and u = ‘0’) then
r <= r - 1;
else
r <= r;
end if;
end if;
end process;
end arch;

 

[FvM]

Which information have you been searching on the web? There are two aspects involved, I think:
- learning VHDL syntax
- learning how digital logic works
Having basic clue of both, the function of the codes should be quite obvious.

Your guesses are correct however. More specifically, the second VHDL code is a behavioral description of an up-/down counter with asynchronous and synchronous reset.

P.S.: A VHDL text book like Enoch, Digital Logic and Microprocessor Design With VHDL should be helpful.
More suggestion are here https://www.edaboard.com/threads/132597/#post578184

 

[mr_l]

I've been trying to figure out what exactly the specified code says about these circuits
ie the type of circuits code describes and what these circuits does.Have read a bit more about digital circuits and VHDL last days.
As I understand the code in the first case could be som type of simple checker
which determines if the input values represents even or odd value.

is this possible????

architecture rtl of D2a is
begin
process (X0, X1, X2)
begin
case (X0 & X1 & X2) is
when "100" => z <= '1';
when "010" => z <= '1';
when "001" => z <= '1';
when "101" => z <= '1';
when others => z <= '0';
end case;
end process;
end D2a;

 

[TrickyDicky]

it isnt checking for odd/even. Its just a decoder, with 4 out of 8 states set to '1' (in this case, 1, 2, 4, 5)