What tool should be used to simulate a DFT design?

[irun2]

Dear all,
Can somebody tell me what tool to be used if I want to simulate a design after DFT insertion? Is that tetraMAX?

Thx in advance!

 

[poluekt]

tetraMAX is used for generation test patterns. Write patterns in verilog format and simulate with netlist in your verilog simulator.

 

[ivlsi]

Is the TetraMax able to write the Test Patterns out in the Verilog format?

Is it MUST to simulate test patterns on the Netlist? Why?

 

[rca]

Yes tetramax could generate Verilog.
Is it better to confirm that the macro model used to generate the patterns fit the silicium.

---------- Post added at 09:27 ---------- Previous post was at 09:27 ----------

With timing you will check the setup and hold time.

 

[ivlsi]

rca,

you wrote: "better to confirm that the macro model used to generate the patterns fit the silicium" - what does it mean? would you elaborate please? What is a "macro model"? How many do exist?

After Test Patterns generation, is it MUST to run them on the Netlist in order to validate them?

Thank you!

---------- Post added at 13:07 ---------- Previous post was at 12:50 ----------

What tools are used for creation BIST wrappers for Memories?

Is there a tool, which is able to create a BIST Controller? Why sometimes designers write it from the scratch?

Is the BIST Controller managed via JTAG? How might the JTAG Controller be incorporated in the BIST/DFT flow? May the AJTAG Controllers work as a BIST Controller and vice versa?

 

[rca]

By macro model I include analog block (custom), mémoires, pads...
in our internal methodology, we must run the stuck patterns on the timing netlist.
A bits controller could be generate by the DFT tool from Cadence, Mentor, Synopsys or other one EDA vendor.
the Bist could be made by software or hardware is really dependent of your goal, area, power, test time, do you need to redo the Bist after each power up....

 

[ivlsi]

Thank you rca for your reply!

You wrote: "must run the stuck patterns on the timing netlist" - why only the stuck@ faults? What about rest of the faults? why their patterns should not be simulated on the Netlist with timing? Do you run the patterns on both BC and WC corners?

As for the ATPG, is there a sense to generate patters for a stands-alone block (even a big one) or all the ATPG tasks should be run only on the full chip netlist? Should this Netlist include Pads and Memories? Should the ATPG patterns be generated after a BIST logic insertion?

Thank you!

 

[rca]

We run by default the stuck faults, to cover the scan chain connections and some timing checks. In all case, it is better to simulate all patterns, but that will cost a lot of run time.
The netlist should include the pad and memories, and also during the ATPG. You will check the pad mode (bidirectional in correct sens..., pull enable or disable, better to be disabled, to improve speed), the memory could be used by the ATPG (if the memory could have a read or write access) to complete the testability of the memory.....

 

[ivlsi]

Is there a sense to generate patterns for the stand-alone modules/blocks just in case to test their testability?

---------- Post added at 00:49 ---------- Previous post was at 00:42 ----------

the memory could be used by the ATPG (if the memory could have a read or write access) to complete the testability of the memory....."

How ATPG can test Memories? Have you meant BIST or probably Memories, which have an access from the external pins?

 

[rca]

for memory test, I only know for fastscan. If you have the correct memory model, that explain how to write or read, the ATPG could generate pattern to write and read some memory address to test the connection to/from the memory. And for the rom you could also load the contain and the ATPG will generate the read condition.

for the stand-alone module, I don't understand your case. For example, in our design we have a pll with some digital logic to lock/divide.... This module is completly inside the analog module, and it has his own scan chain. Do you mean something similar?

 

[ivlsi]

If you have the correct memory model

What does it mean? Should the model be a gate-level netlist with timing or it might it be just a RTL code with a timing inside (something like a <= #5 b)?

Under 'stands-alone module' I meant "a big design" (let's say a memory or cache controller), which is not yet integrated into a Full Chip RTL or Netlist. So, it stands alone, not as a part of SoC or rest of the system. You can see it as a system itself.
So, is there a sense in trying to generate Test Patterns for such module in order just to see that it has a good fault coverage?
For example, to synthesis such module and do the STA and LEC analysis is not a problem at all. But what regarding ATPG?

Is it possible to generate Test Patterns on the Netlist without Pads?

For example, in our design we have a pll with some digital logic to lock/divide.... This module is completly inside the analog module, and it has his own scan chain.

Is this chain a part of other chain or you handle it as a separate chain?

Thank you!

 

[rca]

virage memory compiler for example generate the .fs_lib model for fastscan which describe how to execute a read or a write in the memory. And fastscan indicate how many memories could be access in read & write and tried to generate pattern for that.

SoC means for me multi-system in one chip, one pad-ring, one pad access for many core, many systems, and these systems could be contain in one netlist.
If for you, SoC means multi chip, each indivudal chips have his own test modes, his own scan modes, or every one follow the JTAG standard.

 

[ivlsi]

rca,

as for me, the SoC is also a single chip with many systems (functionality) ...

As for the Test Patterns, could them be generated on the Netlist which don't include Pads - just to check a fault coverage?

Thank you!

 

[rca]

The patterns are here to test the silicium, so through the pads.
Or do you want to generate the patterns to know the possible coverage of your netlist?

 

[ivlsi]

do you want to generate the patterns to know the possible coverage of your netlist?

Exactly! Let's say I want to know a coverage of the Netlist without Pads.

BTW, could Pads be tested using ATPG Test Patterns or do they require JTAG anyway? Have you seen chips without JTAG?