the memory could be used by the ATPG (if the memory could have a read or write access) to complete the testability of the memory....."
What does it mean? Should the model be a gate-level netlist with timing or it might it be just a RTL code with a timing inside (something like a <= #5 b)?If you have the correct memory model
Is this chain a part of other chain or you handle it as a separate chain?For example, in our design we have a pll with some digital logic to lock/divide.... This module is completly inside the analog module, and it has his own scan chain.
Exactly! Let's say I want to know a coverage of the Netlist without Pads.do you want to generate the patterns to know the possible coverage of your netlist?