kel8157
Full Member level 2
embedded memories?
let's say I have a serial embedded memory in test mode, which is controlled solely via JTAG->TCB or/and a TPR. The memory's timing waveforms is custom-designed with verilog behavior model. How do they generate JTAG waveforms automatically to access the memory? Are there such tools as to digitize the simulated waveforms and back trace all the inputs JTAG pins?
let's say I have a serial embedded memory in test mode, which is controlled solely via JTAG->TCB or/and a TPR. The memory's timing waveforms is custom-designed with verilog behavior model. How do they generate JTAG waveforms automatically to access the memory? Are there such tools as to digitize the simulated waveforms and back trace all the inputs JTAG pins?