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what the command "set_clock_latency" models in DC?

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JesseKing

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set_clock_latency

when using set_clock_latency in DC, what is this command models?
does it models the clock tree latency?
if so, what the command models when adding the option -source?

another question
When using create_generated_clock to create a new clock from a clock with latency, what's the new clock's latency? half of the original one? if so, the two clocks' edge won't be at the same time, and this will cause some violaiton.

thanks

Best regards!!
 

xyt2001640

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set_clock_latency in design compiler

sorry
but i wonder where to get the tool DC?

what is its full name of DC?
 

no_mad

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synopsys create_generated_clock

but i wonder where to get the tool DC?

what is its full name of DC?

DC is Design Compiler from Synopsys. It is very common tools among ASIC engineer.

Ok, this is what I think the answer for Jesse second question.

By default, create_generated_clock creates an ideal clock, just like create_clock. Source latency from the master clock port is inherited. For network latency, if the master clock is ideal, the generated clock will not have network latency, and if the master clock is propagated, the generated clock will have the network latency.

Meaning is depending on the master clock.

Hope it helps :)
 

nittinsharma80

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dc::create_generated_clock latency

set_clock_latency command is used to define the estimated clock insertion delay during synthesis.

This is primarily used during the prelayout synthesis and timing analysis.

The estimated delay number is an approximation of the delay produced by the clock tree network insertion (done during the layout phase).

Latency basicaly is represented by two types, source latency and network latency.

Source latency is the latency from the ideal waveform to the source pin or port and -source option in the set_clock_latency command represents just that only.

Regarding second qn.

When using create_generated_clock to create a new clock from a clock with latency, what's the new clock's latency? its not the half of the original one? Its the same plus the latency due to the generating logic.

Hope it helps
 

JesseKing

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set_clock_latency master

thank u all guys
 

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