What step to run Prime Time?

[GoodMan]

Hi all,

Can someone tell me about STA step?
What step to run Prime Time for STA? synthesis or layout


3Q

 

[wadaye]

Hi GoodMan,

You can run STA after Synthesis or layout. It's depend on your company's flow.

 

[cdncrk]

Hi all,

Can someone tell me about STA step?
What step to run Prime Time for STA? synthesis or layout


3Q

there is a prime time tutorial in SOLD

 

[eda_wiz]

Two types of STA..

pre layout STA --after synthesis
post layout STA ==after layout..

its not just a single step.. lots of iterations are involved to fix all problems

 

[aegean.chou]

Read design
Set environment
Set constrain
Report timing

 

[honeyxyb]

book " Advanced Asic Chip Synthesis " show a normal sta flow about pre/pos layout. You can download from Edaboard.

 

[horzonbluz]

1. Set your PrimeTime env
2. Set your library
3. Read your design and link it to your tech library.
4. Read your clock and constraints.
5. Run PrimeTime to checkand report your paths in your design.

 

[haosg]

when you run post-apr sta, remember you need remove clock uncertainty and latency, and set propagated clock.
and you should set min library for max / min analysis.

 

[spauls]

Better go through Prime TIme manual, rather than going thru books

 

[kelvin_sg]

The flow I did was as follows,

...Set library
...Set working environment
...Read in netlist
...Souce constraint file
...Annotate SDF file, either from P&R or design compiler
...Report timing and violations
...Done


HTH
Kelvin

 

[AlexWan]

<Advance Chip Synthesis>2nd

I think it is a good guide.

h**p://

 

[ken_ooi]

For post-route STA, you might need to read in the SPEF also.

 

[allanweee]

I use PT for whole chip timing report even in presim or postsim.

 

[sxqzj]

Does it needs STA prelayout ?maybe it's a optional ,but i think it's not useful !

 

[satya]

How Prime Time does the prelayout STA. Can anybody point me too some good appnote for Static Timing Analysis.

Thanks
Satya

 

[rakko]

If you have access to synopsys solvenet web site. search for STA. they have lots of example scripts and app notes on their web site.

 

[armmips]

It is very useful. Thanks for your sharing.

 

[wakki1187]

do we need to generate .sdf file for a combinational circuit to check the path delay?