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Does DFT C can deal with the coverage estimation completly?
now i encountered a problem when i use estimate_test_coverage,and the log infos show that u should set_test_simulation_library first. i dont know what library it means? where can i get it?
anyone can show me the detailed procedure for this problem?
i am an newer, thanks everybody!
The test_simulation_library is the verilog library used by DFTC or TetraMAX (which, if you have it, is the preferable way to get your fault coverage) to model your circuit. Could be standard cell libraries, for example.
If you have DFTC, consult the doc tree for the best procedure. I think it varies according to version - for example, I think the command 'estimate_test_coverage' is deprecated in XG mode.
Don't get confused between a Synopsys library, as in '.lib', and a verilog library (which is normally used for simulation, and is a '.v' file containing a module for each cell in the library).
In most ASIC library situations, you'll have multiple parallel directories where your tools read different views of the library: there's a synth view, a sim view, a layout view, ATPG view (for ATPG tools that need a special library) etc.
TetraMAX reads the verilog library (sim view, if you will), except in the case of embedded memories, where the 'verilog' syntax is very limited - that's another subject.
What I mean by the doc tree is the sub-directory of the installation directory where the documentation is held. The location will vary from site to site - consult the guy who installs/maintains your EDA tools.