hi, there are many way to learn or to start vhdl i prefer you u should leran designing of verilog programming which is so simple as as c-language vhdl and verilog has same nature of work i am sending you some website address from where i think you can gain good and reasonable knowledge;
as you are abeginner the best book is
PEDRONI..it is simply superb
i dont about vhdl earlier..but i am very familiar with vhdl bcoz of pedroni
for the beginners only it is the best .
to get master in vhdl first try pedroni and then go for other books
BOOKS ON VHDL
! pedroni
2 Perry
3 Smith
4 Bhasker(very good book)
For beginners VHDL Primer by J Bhasker is the best to my knowledge. This book costs around 300/- you can get it cheaper also. Else there is lot of material on the net. Try these files also
hey i have the questions which are asked to me ininterview
!)difference between signsl and variables..not a single defintions ...u have to provide with example
2)generic means
#)configuration means
#)how can u terminate the process
$)sybthesizable and not synthesizable items
%)frequently asked questions in every inter
program for 4:1 mux,,asynchronous and synchronou D FF
&)synthesis results of if and case