What should be the scope of my sdf file?

[bossbebes]

I everybody,


I try to elaborate my gate level netlist and I can not find what should be the scope of my sdf file.
My netlist is from quartus and I elaborate with cadence environment (ncelab).

I have a test bench, made by hand : nce_tpc_tb.vhdl
In this test bench I have :
entity nce_tpc_tb is
end nce_tpc_tb;

architecture firsttime of nce_tpc_tb is

--this is my DUT, gate level netlist
component nce_tpc
port(
....
....
)end component;

--instanciation
inst_nce_tpc_tb : nce_tpc port map (......)


In my sdf file, what will be my scope ( for vhdl file and / or verilog)
Because I always got the same error :
ncelab/SDFSNF =
The SCOPE field from the SDF file list didn't match up with
the design's instance hierarchy.


Thanks a lot .

A confused beginner

 

[ljxpjpjljx]

Re: scope

can you make sure your netlist is matched with your sdf file? ask your backend team guys to get reply!

 

[bossbebes]

Re: scope

Hi ,

Thxs for your reply

What do you mean by : "netlist is matched with your sdf file".
First of all i generate a netlist (.vqm) with symplify_pro, then I genete the final netlist + delay (sdo, vho) thanks to quartus software.

I guss that my netlist should matched with my sdf file, but how can I be sure ?


Thx

++