two important points should be take attention to when design such a fifo.
first, output data rate of the fifo should match to input data rate,otherwise, the fifo depth will be finate
as the average input data rate is always bigger than
output data rate.
you can use this equation to check whether the fifo
depth is infinite:
(A/B)*W_CLK*w_datawidth=(X/Y) * R_CLK*r_datawidth (1)
w_clk denotes the write clock frequency of fifo
r_clk denotes the read clock frequency of fifo
in write clock domain ,A datas is writen into fifo during B clock cycles.
in read clock domain ,x datas is writen into fifo during y clock cycles.
w_datawidth denotes write data bit width.
A/B means write link bandwidth utilization rate of fifo.
w_CLK*w_datawidth means write link bandwidth .
x/y means write link bandwidth utilization rate of fifo.
r_CLK*r_datawidth means read link bandwidth .
the equation (1) means output data throughput of the fifo should match to input data throughput.
second, the minimum fifo depth.
you can use equation (2) to get your fifo depth.
fifo_depth = burst_length - burst_length * (X/Y) * (r_clk/w_clk) *(r_datawidth/w_datawidth) (2)
make a little change to this equation then you can get :
fifo_depth = burst_length - (burst_length /w_clk)*[r_clk*(x/y)*(r_datawidth/w_datawidth)]
(burst_length /w_clk) means how long time does this write burst keeps.
r_clk*(x/y)*(r_datawidth/w_datawidth) means the actual read rate.
so the product of them means quantity of datas read out during the time when write burst keeps on going into the fifo.