What part is assert argument

[ruwan2]

Hi,

I read verilog-ams LRM. I do not find 'assert argument' in the book on the following passage:

Using the assert argument, the output of the integration operator can be reset to a given value at any time.
This feature is demonstrated in the following model, which uses the idt() operator to generate a periodic
ramp waveform:
module ramp_generator(out);
output out;
voltage out;
integer reset;
analog begin
reset = 0;
@(timer(1, 1))
reset = 1;
V(out) <+ idt(1.0, 0, reset);
end
endmodule

Is it '@(timer(1, 1))? or it is missing?

Thanks,

 

[ads-ee]

I could be wrong but argument seems like the input to a operator/function/task type thing..
Using the assert argument, the output of the integration operator can be reset to a given value at any time.
This feature is demonstrated in the following model, which uses the idt() operator to generate a periodic
ramp waveform:

V(out) <+ idt(1.0, 0, reset);

Hmm, the idt() operator (integration?) has a reset argument