what next after tspice simulation

[ksrinivasan]

tspice simulation

hi friends

iam doing a work on digital asic implementation .The backend tool is tanner.my flow till now is VHDL-->synthesis(Leo spec)-->edif-->tanner SPR-->Place and route-->DRC-->netlist extraction-->T spice simulation/Wedit waveform viewer-->What next and how??

in many flows they have given LVS.
I am unable to understand the role of LVS in digital design flow as i have no schematic drawn till now

Thanks in advance
Srinivas

 

[rob1012]

you don't need lvs because you used auto place and route from tanner.. you use lvs when you create a schematic and manually place and route ur design and verify that they are equal( schematic and layout). Basically, ur finished with your design.

 

[rob1012]

hi,

if you have the layout output from the auto place and route step you did, you just need to convert it to gdsII format. if your using tanner, there is an option there to export mask data to GDSII format.. hope this helps.