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hi, chip123, thank you very much!
this design is a interface of a adc.
that adc is inverse, so, for avoiding ip entanglemant, it must modify some parts such as interface.
i have synthesised the design and simulate it by hspice, i don't know what other works must do.
for i do front-end work ago and don't touch back-end work, so, i can't conform whether i do correct and integrity.
you chip is ms. i think you must do final simulate with rc (post-sim) after layout. this is for whole chip, not a block only. and you would doing something about test.
all this things are doing by front-end, not back-end. normally.
If you are finished with the coding and simulation, then first of all you should read the manual of the synthesis tool which you are using. It will tell you about all the steps. You can get the updated manuals from Xilinx, Altera and Mentor Graphics' Leonardo Spectrum from their websites. MultiSim is another very good tool which provides mixed signal simulation.
I'm familliar with FPGA design, and i did a small project for ASICs. My question is about the P&R and de Maks design for ASIC (CMOS technologie at any level) what are the tools that i have to use??? For the Mask design, is it an automated process, or i have to do it buy hand???? Thanks for your help
After synthesis, You can
1. go home and sleep
2. you can do more(endless) work including FV, DFT, CKgen, P&R, Postsim, STA ......
If you are doing Mixed Signal, then try Hspice(use Nanosim/Hsim/Starsim if ur design are too large) simulation at transistor level.(yes, your digital CMOS gates are transistors indeed)
A design flow is a sequence of steps to design an ASIC
1. Design entry. Using a hardware description language (HDL) or schematic entry.
2. Logic synthesis. Produces a netlist—logic cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and blocks.
8. Extraction. Determine the resistance and capacitance of the interconnect.
9. Postlayout simulation. Check to see the design still works with the added loads of the
i think it is decided by you aim !
often i syntheis the vhdl code to see the timing and source usage!
we can see if the source usage is reasonable or not and the time consuming is too long! we can take place some wire or something else[/code]
After synthesis you do scan insertion and then generate your ATPG test vectors. Then you take the netlist to backend P&R, then you do post-layout timing analysis and physical verification. You have to do formal verification after every stage to make sure the netlist has the same functionality.