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what may i do after synthesis?

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wolfkin

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hi, dear all,
i have synthesis the my design. but, i don't know what i may do in future, please someone tell me!
thanks!
 

C

chip123

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Dear wolfkin,

Then why did you do synthesis for?:)
After synthesis, you may do one of below according to requirement:
1. Post-Simualtion
2. FPGA verification
3. Layout APR

Regards,
chip123
 

wolfkin

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hi, chip123, thank you very much!
this design is a interface of a adc.
that adc is inverse, so, for avoiding ip entanglemant, it must modify some parts such as interface.
i have synthesised the design and simulate it by hspice, i don't know what other works must do.
for i do front-end work ago and don't touch back-end work, so, i can't conform whether i do correct and integrity.

thanks & best regards!
wolfkin
 

aegean.chou

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for ASIC project, you should:

1)Formal verify or Simulation

2)Clock tree generate

3)Place and route

4)DRC + LVS

5)Formal verify or Simulation

6)Timing analyse
 

z81203

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you chip is ms. i think you must do final simulate with rc (post-sim) after layout. this is for whole chip, not a block only. and you would doing something about test.
all this things are doing by front-end, not back-end. normally.
regards.
 

wolfkin

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thanks very much!
i'll do those!

to, aegean.chou, are you a chinese? i am!

thansks & best regards!
wolfkin
 

melonpy

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Dear wolfkin
Why do think aegean are chinese??? :)
How do you do the mixed-signal simulation to your design? By which tools?
 

wolfkin

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by aegean's nickname!
the name separate by a dot, and the posfix part is chou that is zhou in chinese, but, in general, chou don't rgard a name in english.
so, i think aegean is a chinese.
ok?

best regards!
wolfkin
 

maniasonic

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for digital logic, you don't have to simulate by spice. just a post-synthesis simulation at HDL level is enough!
 

honey

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TAPE OUT NET TO PLACE ROUTE
 

sandusty

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Hi, Wolfkin:

You could run your gate level simulation before you start your auto place&route or put into an FPGA. If you make the scan insertion, you can start your ATPG.

Of coures, you should check your synthesis log first. Check the timing violations, area, cell usage .... make sure your syntheser finished the job as what you want... :)
 

faisalali

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If you are finished with the coding and simulation, then first of all you should read the manual of the synthesis tool which you are using. It will tell you about all the steps. You can get the updated manuals from Xilinx, Altera and Mentor Graphics' Leonardo Spectrum from their websites. MultiSim is another very good tool which provides mixed signal simulation.
 

jacklalo020

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Hi,
I'm familliar with FPGA design, and i did a small project for ASICs. My question is about the P&R and de Maks design for ASIC (CMOS technologie at any level) what are the tools that i have to use??? For the Mask design, is it an automated process, or i have to do it buy hand???? Thanks for your help
 

sweesw

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wolfkin said:
hi, dear all,
i have synthesis the my design. but, i don't know what i may do in future, please someone tell me!
thanks!

After synthesis, You can
1. go home and sleep
2. you can do more(endless) work including FV, DFT, CKgen, P&R, Postsim, STA ......
If you are doing Mixed Signal, then try Hspice(use Nanosim/Hsim/Starsim if ur design are too large) simulation at transistor level.(yes, your digital CMOS gates are transistors indeed)
 

dada1019

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A design flow is a sequence of steps to design an ASIC
1. Design entry. Using a hardware description language (HDL) or schematic entry.
2. Logic synthesis. Produces a netlist—logic cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and blocks.
8. Extraction. Determine the resistance and capacitance of the interconnect.
9. Postlayout simulation. Check to see the design still works with the added loads of the
interconnect.
 

badboypym

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hi
i think it is decided by you aim !
often i syntheis the vhdl code to see the timing and source usage!
we can see if the source usage is reasonable or not and the time consuming is too long! we can take place some wire or something else[/code]
 

killbuz

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Hi,
After synthesis you do scan insertion and then generate your ATPG test vectors. Then you take the netlist to backend P&R, then you do post-layout timing analysis and physical verification. You have to do formal verification after every stage to make sure the netlist has the same functionality.
Thanks,
 

dynoboy

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I have loved Honey 's reply this guy says tape out...AMAZING honey keep it up
 

O

omiga

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pre-layout simulation
pre-layout timing analyze
post-layout
post-layout simulation
post-layout timing analyze
 

delay

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You do timing to verify behavior before getting to physical.
 

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