What is your bottom-neck issue in your designs?

[analyisisman]

bottom neck

I am working on an article writing for EDA industry. Please help:
you can pick one or more or give point(s) I don't list below. Thanks.

1. PCB Layout - Rule setting/check
2. PCB Layout - Routing
3. PCB Layout - team work capability
4. PCB Layout - ReUse capability
5. Package - Rule setting/check
6. Package - Routing
7. Package - team work capability
8. Package - ReUse capability
9. Signal integrity - simulator capability
10. Signal integrity - simulation speed
11. Signal integrity - simulator accuracy
12. Signal integrity - field solver capability
13. Signal integrity - field solver speed
14. Signal integrity - field solver accuracy
15. Signal integrity - post processing capability
16. System integrations - PCB & Packaging
17. System integrations - PCB & SI Analysis
18. System integrations - Packaging & SI
19. SI Modeling - generations
20. SI Modeling - validations
21. SI Modeling - sources
22. SI Modeling - standards

I am trying to list as many as I can. however, they should not cover all. Please give your comments.

Thanks,

 

[majnoon]

bottom-neck

I say all of above...
You have left out few major parts:

1) Schematic changes and "corrections"

2) Placement

3) Mechanical design (Outline, Position of connectors, MHs, Shields so forth...)

Not having any of above steps finalized and agreed on can cause huge issues during layout.

Cheers,

M