What is wrong with this Verilog code? Help! I am a newbie

[buzzerflyer]

module (img, m, v, reset, clk, nimg);
input reset, clk;
input [7:0] img, m, v; //img = I(x,y)
//m=mean
//v=variance
output nimg;
reg [1:0] y, Y;
parameter [1:0] S0=2'b00, S1=2'b01, S2=2'b10;

//NS Logic and Image Normalization Submodule
always @ (img or y)
begin
case
S0: if (img>m) Y=S1; else Y=S2;
S1: nimg=m+sqroot(v.img^2/v); Y=S0;
S2: nimg=m-sqroot(v.img^2/v); Y=S0;
endcase
end


//State register submodule
always @ (negedge reset or posedge clk)
if (!reset) y<=S0;
else y<=Y;

endmodule

 

[shyam4908]

Re: What is wrong with this Verilog code? Help! I am a newbi

looking at the code i think u u missed "m" in the sensitivity list..let me know the exact problem

 

[dilinx]

Re: What is wrong with this Verilog code? Help! I am a newbi

i think u missed the module name.....

 

[devas]

Re: What is wrong with this Verilog code? Help! I am a newbi

And you did not register the output.

And you must use begin - end when using multiple statements (in a case choice).

Devas

 

[buzzerflyer]

i think u missed the module name.....

okay, i have put the module name

module normalize (img, m, v, reset, clk, nimg);
input reset, clk;
input [7] img, m, v; //img = I(x,y)
//m=mean
//v=variance
output nimg;
reg [1] y, Y;
parameter [1] S0=2'b00, S1=2'b01, S2=2'b10;

//NS Logic and Image Normalization Submodule
always @ (img or y)
begin
case
S0: if (img>m) Y=S1; else Y=S2;
S1: nimg=m+sqroot((v*(img-m)*(img-m))/v); Y=S0;
S2: nimg=m-sqroot((v*(img-m)*(img-m))/v); Y=S0;
endcase
end


//State register submodule
always @ (negedge reset or posedge clk)
if (!reset) y<=S0;
else y<=Y;

endmodule

Added after 11 minutes:

help me, please.... i'm beggin you

 

[dilinx]

Re: What is wrong with this Verilog code? Help! I am a newbi

As devas said u must register any variable to use it in always statement and group multiple statements using begin and end keywords in case statement

 

[shitansh]

Re: What is wrong with this Verilog code? Help! I am a newbi

module normalize (img, m, v, reset, clk, nimg);
input reset, clk;
input [7] img, m, v; //img = I(x,y)
//m=mean
//v=variance
output nimg;
reg nimg;
reg [1] y, Y;
parameter [1] S0=2'b00, S1=2'b01, S2=2'b10;

//NS Logic and Image Normalization Submodule
always @ (img or y)
begin
case
S0: if (img>m) Y=S1; else Y=S2;
S1: beginnimg=m+sqroot((v*(img-m)*(img-m))/v); Y=S0;end
S2: beginnimg=m-sqroot((v*(img-m)*(img-m))/v); Y=S0;end
default : begin Y = S0; nimg = 1'b0; end

endcase
end


//State register submodule
always @ (negedge reset or posedge clk)
if (!reset) y<=S0;
else y<=Y;

endmodule

Any way coding style you adoped is not good. For more complex design you will stuck with this kind of style.

HTH

 

[shyam4908]

Re: What is wrong with this Verilog code? Help! I am a newbi

I modified your code and is below

module normalize
(
input reset,
input clk,

input [7] img, //w.r.t u r code i am assuming these as 8bit
input [7] m, //w.r.t u r code i am assuming these as 8bit
input [7] v, //w.r.t u r code i am assuming these as 8bit
output reg nimg //
);

//state machine declaration
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;

reg [1] y, Y; // This is 2bit a you have 3 satetes

//=============================================================================
//NS Logic
always@(reset or img or y or m or v)
begin
if (reset)
Y <= S0; //initial state
else
case
//
S0 : begin
if (img > m )
Y = S1;
else
Y = S2;
end
//
S1 : begin
Y = S0;

end
//
S2 : begin
Y = S0;
nimg=m+sqroot((v*(img-m)*(img-m))/v);
end
endcase
end

//=============================================================================
// output assign menr
always@(posedge clk)
begin
if (!reset)
nimg <= 1'b0; //assuming it is 1-bit
else
case
S0 : nimg <= nimg;
S1 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
S2 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
default : nimg <= nimg;
endcase
end

//=============================================================================
//state assign ment
always@(posedge clk or negedge reset)
begin
if (!reset)
y <= S0;
else
y <= Y;
end
//=============================================================================

endmodule

here i am assuming few things and coded it.. you need to find the componet for sqrroot and other if u get any errors

Added after 2 minutes:

Delete the nming code from the next logic... otherwise u will get multi-drive error

Added after 49 seconds:

module normalize
(
input reset,
input clk,

input [7:0] img, //w.r.t u r code i am assuming these as 8bit
input [7:0] m, //w.r.t u r code i am assuming these as 8bit
input [7:0] v, //w.r.t u r code i am assuming these as 8bit
output reg nimg //
);

//state machine declaration
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;

reg [1:0] y, Y; // This is 2bit a you have 3 satetes

//=============================================================================
//NS Logic
always@(reset or img or y or m or v)
begin
if (reset)
Y <= S0; //initial state
else
case
//
S0 : begin
if (img > m )
Y = S1;
else
Y = S2;
end
//
S1 : begin
Y = S0;

end
//
S2 : begin
Y = S0;
end
endcase
end

//=============================================================================
// output assign menr
always@(posedge clk)
begin
if (!reset)
nimg <= 1'b0; //assuming it is 1-bit
else
case
S0 : nimg <= nimg;
S1 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
S2 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
default : nimg <= nimg;
endcase
end

//=============================================================================
//state assign ment
always@(posedge clk or negedge reset)
begin
if (!reset)
y <= S0;
else
y <= Y;
end
//=============================================================================

endmodule

 

[shitansh]

Re: What is wrong with this Verilog code? Help! I am a newbi

I modified your code and is below

module normalize
(
input reset,
input clk,

input [7:0] img, //w.r.t u r code i am assuming these as 8bit
input [7:0] m, //w.r.t u r code i am assuming these as 8bit
input [7:0] v, //w.r.t u r code i am assuming these as 8bit
output reg nimg //
);

//state machine declaration
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;

reg [1:0] y, Y; // This is 2bit a you have 3 satetes

//=============================================================================
//NS Logic
always@(reset or img or y or m or v)
begin
if (reset)
Y <= S0; //initial state
else
case
//
S0 : begin
if (img > m )
Y = S1;
else
Y = S2;
end
//
S1 : begin
Y = S0;

end
//
S2 : begin
Y = S0;
end
endcase
end

//=============================================================================
// output assign menr
always@(posedge clk)
begin
if (!reset)
nimg <= 1'b0; //assuming it is 1-bit
else
case (Y) //
S0 : nimg <= nimg;
S1 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
S2 : nimg <= m+sqroot((v*(img-m)*(img-m))/v);
default : nimg <= nimg;
endcase
end

//=============================================================================
//state assign ment
always@(posedge clk or negedge reset)
begin
if (!reset)
y <= S0;
else
y <= Y;
end
//=============================================================================

endmodule

Good approach, but unfortunatly there is one clock cycle latency in the output, between origianl code and one you modified.

See correction in bold latter, now this code produce same output as it in original code.

HTH