joshi
Newbie level 3
Hi
'm having ADC chip "ADS 8364" wit 25M Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process.
my problem is before writing vhdl Code i want generate timings ADC to FPGA but
(1) i don no what is this timing generation ?
(2) why this is necessary before Code ?
(3)Can any one give example timing code generation for ADC's
Waiting for all yur Inputs
Joshi
'm having ADC chip "ADS 8364" wit 25M Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process.
my problem is before writing vhdl Code i want generate timings ADC to FPGA but
(1) i don no what is this timing generation ?
(2) why this is necessary before Code ?
(3)Can any one give example timing code generation for ADC's
Waiting for all yur Inputs
Joshi