Dec 15, 2009 #1 J joshi Newbie level 3 Joined Dec 10, 2009 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location bangalore Activity points 1,313 Hi 'm having ADC chip "ADS 8364" wit 25M Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process. my problem is before writing vhdl Code i want generate timings ADC to FPGA but (1) i don no what is this timing generation ? (2) why this is necessary before Code ? (3)Can any one give example timing code generation for ADC's Waiting for all yur Inputs Joshi
Hi 'm having ADC chip "ADS 8364" wit 25M Hz input Clock . ADC output Signal Going to FPGA and its out signal going to processor fr further process. my problem is before writing vhdl Code i want generate timings ADC to FPGA but (1) i don no what is this timing generation ? (2) why this is necessary before Code ? (3)Can any one give example timing code generation for ADC's Waiting for all yur Inputs Joshi