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what is time scale in veilog, defines and why it is used for

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lordsathish

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Hi could any one tell me what is time scale in veilog... what it defines and why it is used for...
Thanks in Advance
 

rakko

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verilog timescale

Normally a simulator advances time with its own internal clock. Verilog allows different timescales mappings from simulator timesteps to real time to be assigned to each module. The `timescale directive is used for this purpose.

Parameters are defined for clarity and ease of code maintenance. The idea is to give constants meaningful names to make your code easier to maintain and understand by others.
 

funster

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verilog $time

it is for time control, when you want to delay a signal by 1 time unit,

then the time unit must be defined, this is timescale.

best regards




lordsathish said:
Hi could any one tell me what is time scale in veilog... what it defines and why it is used for...
Thanks in Advance
 

rakko

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timescale

Does anyone understand what he is talking about here? Or is it me.


//it is for time control, when you want to delay a signal by 1 time unit,
//
//then the time unit must be defined, this is timescale.

what!
 

FLEXcertifydll

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`timescale verilog

based on ur simulation model of the hard-core

ex: ADPLL
 

kappajacko

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time scale in verilog

`timescale time_unit/time_precision

Delays are multiples of time_unit rounded to time_precision.

i.e.

`timescale 10ns/1ns
#1.55 a = b;
'a' gets 'b' after 16 ns because 10ns*1.55 = 15.5 ns = 16ns rounded to nearest 1ns

`timescale 1ns/1ps
#1.00055 a = b;
'a' gets 'b' after 1.0006 ns because 1ns*1.00055ns = 1.00055ns = 1.0006ns rounded to the nearsest pico second
 

asicengineer1

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Time scale in verilog

@kappajacko

First eg. is correct, but i think the second one works out to only 1ns and not 1.0006. Correct me if i'm wrong
 

sandesh564_123

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Re: Time scale in verilog

@kappajacko

i think in second example it ll be 1.001 ns...
 

haytham

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Re: Time scale in verilog

time scale defines time unit / time step
 

veer110

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@ kappajacko : Thanks, too good explanation. :)
 

tariq786

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very good thread. I need to refresh verilog from time to time and this helps me.
 

chandrakanenator

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`timescale 10ns/100ps
module clk;
reg clk_1,clk_2;

initial
begin
clk_1=1'b0;
end
always #10.10 clk_1=~clk_1;


according to this timescale the clk will toggle after 10.10 * (10ns/100ps) units i.e. 1010 units .

So to generalise it, no matter what what is the unit of time just divide the timescale the value you get,multiply it to the delay.And the signal you are delaying would toggle after that much units of time.

-chandrakant
 

dave_59

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What chandrakant says is correct if there is only one timescale precision (i.e. all 100ps). As soon there there are multiple precisions, it gets slightly more complicated.

It might help to understand that Verilog is defined with discrete event-driven simulation semantics. That means time is defined as an integer, and all signal changes (events) scheduled for a later time are put into queues. A queue for a discrete time in the future is created as soon as an event needs to be scheduled for that time. As soon as all the events for the current time are finished, the simulator looks for the next time when an event is scheduled, advances the current time to that next time, and the process repeats until there is nothing left to do, or it executes a $finish. Time is discrete because the simulator only executes the times where events are scheduled, and skips over everything else. So you could have a simulation that executes at times 0,2,5,10,15,20,25,26.
The simulator knows nothing about seconds or nanoseconds, only unit-less integers.

In order to synchronize the scheduling of events across different timescales and precisions, the simulator picks the smallest time precision across the entire design and assigns that the value of 1 time unit. If the smallest precision was 10ps, that becomes the global value of 1 time unit. In the example above, there would be one more scaling applied as the entire design was elaborated, and #10.10 would become a delay of 10100 units. So the statement clk_1 = !clk_1 would be scheduled 10100 units into the future.
 

krishna2728

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'timescale directive is a compiler directive.It is used to measure simulation time or delay time. Usage : `timescale / reference_time_unit : Specifies the unit of measurement for times and delays. time_precision: specifies the precision to which the delays are rounded off.

Timescale directive tends to make more sense at gatelevel simulation than at RTL simulation.
 

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