What is the VREF signal in FPGA with JTAG? Can we change freq. of crystal oscillator?

[mikee]

Hi i am working on Xilinx FPGA Spartan 3E version i have following queries:

1. Crystal Oscillators SG8002DC/ SG8002JF
These are available with their certain frequency i-e 50Mhz in FPGA Kit as a clock generator. Can we change the frequency to our desired value? like if we want to have a Crystal Oscillator SG8002DC/ SG8002JF with 20MHz frequency..... Could it be done programmably? or We should ask supplier to fix frequency to 20Mhz? ??? or what??

2.There is VREF signal in FPGA with JTAG and this signal is connected with FPGA banks... What is this signal all about? Whats its purpose? and What if we are not using the required FPGA Banks then what should we do with that particular signal in JTAG? I have read in Xilinx Spartan3E tutorial that we should not let it unused we have to pass VREF to some other part......

 

[FvM]

FPGA Basic

1. You should get you a crystal oscillator with the intended frequency, e.g. 20 MHz. Alternatively, you can use a 50 MHz clock and generate 20 MHz by a PLL in the FPGA. SG-8002 is actually a programmable oscillator, but you need blank osillator devices and a special SG-Writer to program them on your own. I guess, it's not reasonable for your purpose.

2. VREF is telling the JTAG adapter about the correct supply voltage for the interface. It has to be connected to the I/O voltage of the FPGA bank, where the JTAG pins belong to, typically 3.3V

 

[mikee]

FPGA Basic

1. Its SG8002DC/JF is programmable so can we programme it by using Xilinx sysnthesizer? and how can we do it by using PLL??

2. FPGA banks have several VREF pins(signals..) What if we dont wana use it???? or tell me that which pins(FPGA components) are these(VREF) to be connected so that it won't effect the logic at all....

Am i clear to you in defining my problem?

 

[FvM]

FPGA Basic

In both cases, I suggest to consult respective product literature. Blank SG-8002 devices are one-time programmable in production, not in-system programmable. The concept of clock processing with PLLs is widely discussed in Xilinx datasheets and applications notes, it doesn't make much sense to repeat it here.

JTAG "VREF" is another thing than "VREF" of voltage refernced IO-standards. As I said, JTAG VREF has to be connected to a supply voltage. VREF pins in various IO banks is used e.g. for DDR RAM interfaces.