#### Cesar0182

##### Member level 4

Code:

```
// Make sure the memory is implemented as distributed
(* rom_style = "distributed" *)
reg [38:0] rom [63:0]; // 39 bit word 64 words deep
initial begin
// rom entries contain (in order) the address, a bitmask, and a bitset
//***********************************************************************
// State 1 Initialization
//***********************************************************************
// Store the power bits
rom[0] = {7'h28, 16'h0000, 16'hFFFF};
// Store CLKOUT0 divide and phase
rom[1] = (S1_CLKOUT0_FRAC_EN == 0) ?
{7'h09, 16'h8000, S1_CLKOUT0[31:16]}:
{7'h09, 16'h8000, S1_CLKOUT0_FRAC_CALC[31:16]};
rom[2] = (S1_CLKOUT0_FRAC_EN == 0) ?
{7'h08, 16'h1000, S1_CLKOUT0[15:0]}:
{7'h08, 16'h1000, S1_CLKOUT0_FRAC_CALC[15:0]};
// Store CLKOUT1 divide and phase
rom[3] = {7'h0A, 16'h1000, S1_CLKOUT1[15:0]};
rom[4] = {7'h0B, 16'hFC00, S1_CLKOUT1[31:16]};
// Store CLKOUT2 divide and phase
rom[5] = {7'h0C, 16'h1000, S1_CLKOUT2[15:0]};
rom[6] = {7'h0D, 16'hFC00, S1_CLKOUT2[31:16]};
// Store CLKOUT3 divide and phase
rom[7] = {7'h0E, 16'h1000, S1_CLKOUT3[15:0]};
rom[8] = {7'h0F, 16'hFC00, S1_CLKOUT3[31:16]};
// Store CLKOUT4 divide and phase
rom[9] = {7'h10, 16'h1000, S1_CLKOUT4[15:0]};
rom[10] = {7'h11, 16'hFC00, S1_CLKOUT4[31:16]};
// Store CLKOUT5 divide and phase
rom[11] = {7'h06, 16'h1000, S1_CLKOUT5[15:0]};
rom[12] = (S1_CLKOUT0_FRAC_EN == 0) ?
{7'h07, 16'hC000, S1_CLKOUT5[31:16]}:
{7'h07, 16'hC000, S1_CLKOUT5[31:30], S1_CLKOUT0_FRAC_CALC[35:32],S1_CLKOUT5[25:16]};
// Store CLKOUT6 divide and phase
rom[13] = {7'h12, 16'h1000, S1_CLKOUT6[15:0]};
rom[14] = (S1_CLKFBOUT_FRAC_EN == 0) ?
{7'h13, 16'hC000, S1_CLKOUT6[31:16]}:
{7'h13, 16'hC000, S1_CLKOUT6[31:30], S1_CLKFBOUT_FRAC_CALC[35:32],S1_CLKOUT6[25:16]};
// Store the input divider
rom[15] = {7'h16, 16'hC000, {2'h0, S1_DIVCLK[23:22], S1_DIVCLK[11:0]} };
// Store the feedback divide and phase
rom[16] = (S1_CLKFBOUT_FRAC_EN == 0) ?
{7'h14, 16'h1000, S1_CLKFBOUT[15:0]}:
{7'h14, 16'h1000, S1_CLKFBOUT_FRAC_CALC[15:0]};
rom[17] = (S1_CLKFBOUT_FRAC_EN == 0) ?
{7'h15, 16'h8000, S1_CLKFBOUT[31:16]}:
{7'h15, 16'h8000, S1_CLKFBOUT_FRAC_CALC[31:16]};
// Store the lock settings
rom[18] = {7'h18, 16'hFC00, {6'h00, S1_LOCK[29:20]} };
rom[19] = {7'h19, 16'h8000, {1'b0 , S1_LOCK[34:30], S1_LOCK[9:0]} };
rom[20] = {7'h1A, 16'h8000, {1'b0 , S1_LOCK[39:35], S1_LOCK[19:10]} };
// Store the filter settings
rom[21] = {7'h4E, 16'h66FF,
S1_DIGITAL_FILT[9], 2'h0, S1_DIGITAL_FILT[8:7], 2'h0,
S1_DIGITAL_FILT[6], 8'h00 };
rom[22] = {7'h4F, 16'h666F,
S1_DIGITAL_FILT[5], 2'h0, S1_DIGITAL_FILT[4:3], 2'h0,
S1_DIGITAL_FILT[2:1], 2'h0, S1_DIGITAL_FILT[0], 4'h0 };
//***********************************************************************
// State 2 Initialization
//***********************************************************************
// Store the power bits
rom[23] = {7'h28, 16'h0000, 16'hFFFF};
// Store CLKOUT0 divide and phase
rom[24] = (S2_CLKOUT0_FRAC_EN == 0) ?
{7'h09, 16'h8000, S2_CLKOUT0[31:16]}:
{7'h09, 16'h8000, S2_CLKOUT0_FRAC_CALC[31:16]};
rom[25] = (S2_CLKOUT0_FRAC_EN == 0) ?
{7'h08, 16'h1000, S2_CLKOUT0[15:0]}:
{7'h08, 16'h1000, S2_CLKOUT0_FRAC_CALC[15:0]};
// Store CLKOUT1 divide and phase
rom[26] = {7'h0A, 16'h1000, S2_CLKOUT1[15:0]};
rom[27] = {7'h0B, 16'hFC00, S2_CLKOUT1[31:16]};
// Store CLKOUT2 divide and phase
rom[28] = {7'h0C, 16'h1000, S2_CLKOUT2[15:0]};
rom[29] = {7'h0D, 16'hFC00, S2_CLKOUT2[31:16]};
// Store CLKOUT3 divide and phase
rom[30] = {7'h0E, 16'h1000, S2_CLKOUT3[15:0]};
rom[31] = {7'h0F, 16'hFC00, S2_CLKOUT3[31:16]};
// Store CLKOUT4 divide and phase
rom[32] = {7'h10, 16'h1000, S2_CLKOUT4[15:0]};
rom[33] = {7'h11, 16'hFC00, S2_CLKOUT4[31:16]};
// Store CLKOUT5 divide and phase
rom[34] = {7'h06, 16'h1000, S2_CLKOUT5[15:0]};
rom[35] = (S2_CLKOUT0_FRAC_EN == 0) ?
{7'h07, 16'hC000, S2_CLKOUT5[31:16]}:
{7'h07, 16'hC000, S2_CLKOUT5[31:30], S2_CLKOUT0_FRAC_CALC[35:32],S2_CLKOUT5[25:16]};
// Store CLKOUT6 divide and phase
rom[36] = {7'h12, 16'h1000, S2_CLKOUT6[15:0]};
rom[37] = (S2_CLKFBOUT_FRAC_EN == 0) ?
{7'h13, 16'hC000, S2_CLKOUT6[31:16]}:
{7'h13, 16'hC000, S2_CLKOUT6[31:30], S2_CLKFBOUT_FRAC_CALC[35:32],S2_CLKOUT6[25:16]};
// Store the input divider
rom[38] = {7'h16, 16'hC000, {2'h0, S2_DIVCLK[23:22], S2_DIVCLK[11:0]} };
// Store the feedback divide and phase
rom[39] = (S2_CLKFBOUT_FRAC_EN == 0) ?
{7'h14, 16'h1000, S2_CLKFBOUT[15:0]}:
{7'h14, 16'h1000, S2_CLKFBOUT_FRAC_CALC[15:0]};
rom[40] = (S2_CLKFBOUT_FRAC_EN == 0) ?
{7'h15, 16'h8000, S2_CLKFBOUT[31:16]}:
{7'h15, 16'h8000, S2_CLKFBOUT_FRAC_CALC[31:16]};
// Store the lock settings
rom[41] = {7'h18, 16'hFC00, {6'h00, S2_LOCK[29:20]} };
rom[42] = {7'h19, 16'h8000, {1'b0 , S2_LOCK[34:30], S2_LOCK[9:0]} };
rom[43] = {7'h1A, 16'h8000, {1'b0 , S2_LOCK[39:35], S2_LOCK[19:10]} };
// Store the filter settings
rom[44] = {7'h4E, 16'h66FF,
S2_DIGITAL_FILT[9], 2'h0, S2_DIGITAL_FILT[8:7], 2'h0,
S2_DIGITAL_FILT[6], 8'h00 };
rom[45] = {7'h4F, 16'h666F,
S2_DIGITAL_FILT[5], 2'h0, S2_DIGITAL_FILT[4:3], 2'h0,
S2_DIGITAL_FILT[2:1], 2'h0, S2_DIGITAL_FILT[0], 4'h0 };
// Initialize the rest of the ROM
rom[46] = {7'h28,32'h0000_0000};
for(ii = 47; ii < 64; ii = ii +1) begin
rom[ii] = 0;
end
end
```

Code:

```
type array_64x39 is array (63 downto 0) of std_logic_vector(38 DOWNTO 0);
attribute rom_style : string;
SIGNAL rom : array_64x39 register;
attribute rom_style of rom : signal is "distributed";
process
begin
-- Store the power bits
rom(0) <= "0101000" & x"0000" & x"FFFF";
-- Store CLKOUT0 divide and phase
S1_CLKOUT0_FRAC_A <= ("0001001" & x"8000" & S1_CLKOUT0(31 downto 16)) when S1_CLKOUT0_FRAC_EN = 0 else ("0001001" & x"8000" & S1_CLKOUT0_FRAC_CALC(31 downto 16));
rom(1) <= S1_CLKOUT0_FRAC_A;
S1_CLKOUT0_FRAC_B <= ("0001000" & x"1000" & S1_CLKOUT0(15 downto 0)) when(S1_CLKOUT0_FRAC_EN = 0) else ("0001000" & x"1000" & S1_CLKOUT0_FRAC_CALC(15 downto 0));
rom(2) <= S1_CLKOUT0_FRAC_B;
-- Store CLKOUT1 divide and phase
rom(3) <= "0001010" & x"1000" & S1_CLKOUT1(15 downto 0);
rom(4) <= "0001011" & x"FC00" & S1_CLKOUT1(31 downto 16);
-- Store CLKOUT2 divide and phase
rom(5) <= "0001100" & x"1000" & S1_CLKOUT2(15 downto 0);
rom(6) <= "0001101" & x"FC00" & S1_CLKOUT2(31 downto 16);
-- Store CLKOUT3 divide and phase
rom(7) <= "0001110" & x"1000" & S1_CLKOUT3(15 downto 0);
rom(8) <= "0001111" & x"FC00" & S1_CLKOUT3(31 downto 16);
-- Store CLKOUT4 divide and phase
rom(9) <= "0010000" & x"1000" & S1_CLKOUT4(15 downto 0);
rom(10) <= "0010001" & x"FC00" & S1_CLKOUT4(31 downto 16);
-- Store CLKOUT5 divide and phase
rom(11) <= "0000110" & x"1000" & S1_CLKOUT5(15 downto 0);
S1_CLKOUT0_FRAC_C <= ("0000111" & x"C000" & S1_CLKOUT5(31 downto 16)) when (S1_CLKOUT0_FRAC_EN = 0) else ("0000111" & x"C000" & S1_CLKOUT5(31 downto 30) & S1_CLKOUT0_FRAC_CALC(35 downto 32) & S1_CLKOUT5(25 downto 16));
rom(12) <= S1_CLKOUT0_FRAC_C;
-- Store CLKOUT6 divide and phase
rom(13) <= "0010010" & x"1000" & S1_CLKOUT6(15 downto 0);
S1_CLKOUT0_FRAC_D <= ("0010011" & x"C000" & S1_CLKOUT6(31 downto 16)) when (S1_CLKFBOUT_FRAC_EN = 0) else ("0010011" & x"C000" & S1_CLKOUT6(31 downto 30) & S1_CLKFBOUT_FRAC_CALC(35 downto 32) & S1_CLKOUT6(25 downto 16));
rom(14) <= S1_CLKOUT0_FRAC_D;
-- Store the input divider
rom(15) <= "0010110" & x"C000" & ("00" & S1_DIVCLK(23 downto 22) & S1_DIVCLK(11 downto 0));
-- Store the feedback divide and phase
S1_CLKOUT0_FRAC_E <= ("0010100" & x"1000" & S1_CLKFBOUT(15 downto 0)) when (S1_CLKFBOUT_FRAC_EN = 0) else ("0010100" & x"1000" & S1_CLKFBOUT_FRAC_CALC(15 downto 0));
rom(16) <= S1_CLKOUT0_FRAC_E ;
S1_CLKOUT0_FRAC_F <= ("0010011" & x"8000" & S1_CLKFBOUT(31 downto 16)) when (S1_CLKFBOUT_FRAC_EN = 0) else ("0010011" & x"8000" & S1_CLKFBOUT_FRAC_CALC(31 downto 16));
rom(17) <= S1_CLKOUT0_FRAC_F;
-- Store the lock settings
rom(18) <= "0011000" & x"FC00" & ("000000" & S1_LOCK(29 downto 20));
rom(19) <= "0011001" & x"8000" & ('0' & S1_LOCK(34 downto 30) & S1_LOCK(9 downto 0));
rom(20) <= "0011010" & x"8000" & ('0' & S1_LOCK(39 downto 35) & S1_LOCK(19 downto 10));
-- Store the filter settings
rom(21) <= "1001110" & x"66FF" & S1_DIGITAL_FILT(9) & "00" & S1_DIGITAL_FILT(8 downto 7) & "00" & S1_DIGITAL_FILT(6) & x"00";
rom(22) <= "1001111" & x"666F" & S1_DIGITAL_FILT(5) & "00" & S1_DIGITAL_FILT(4 downto 3) & "00" & S1_DIGITAL_FILT(2 downto 1) & "00" & S1_DIGITAL_FILT(0) & x"0" ;
--***********************************************************************
--State 2 Initialization
--***********************************************************************
-- Store the power bits
rom(23) <= "0101000" & x"0000" & x"FFFF";
-- Store CLKOUT0 divide and phase
S1_CLKOUT0_FRAC_G <= ("0001001" & x"8000" & S2_CLKOUT0(31 downto 16))+8
when (S2_CLKOUT0_FRAC_EN = 0) else ("0001001" & x"8000" & S2_CLKOUT0_FRAC_CALC(31 downto 16));
rom(24) <= S1_CLKOUT0_FRAC_G;
S1_CLKOUT0_FRAC_H <= ("0001000" & x"1000" & S2_CLKOUT0(15 downto 0)) when (S2_CLKOUT0_FRAC_EN = 0) else ("0001000" & x"1000" & S2_CLKOUT0_FRAC_CALC(15 downto 0));
rom(25) <= S1_CLKOUT0_FRAC_H;
-- Store CLKOUT1 divide and phase
rom(26) <= "0001010" & x"1000" & S2_CLKOUT1(15 downto 0);
rom(27) <= "0001011" & x"FC00" & S2_CLKOUT1(31 downto 16);
-- Store CLKOUT2 divide and phase
rom(28) <= "0001100" & x"1000" & S2_CLKOUT2(15 downto 0);
rom(29) <= "0001101" & x"FC00" & S2_CLKOUT2(31 downto 16);
-- Store CLKOUT3 divide and phase
rom(30) <= "0001110" & x"1000" & S2_CLKOUT3(15 downto 0);
rom(31) <= "0001111" & x"FC00" & S2_CLKOUT3(31 downto 16);
-- Store CLKOUT4 divide and phase
rom(32) <= "0010000" & x"1000" & S2_CLKOUT4(15 downto 0);
rom(33) <= "0010001" & x"FC00" & S2_CLKOUT4(31 downto 16);
-- Store CLKOUT5 divide and phase
rom(34) <= "0000110" & x"1000" & S2_CLKOUT5(15 downto 0);
S1_CLKOUT0_FRAC_I <= ("0000111" & x"C000" & S2_CLKOUT5(31 downto 16)) when (S2_CLKOUT0_FRAC_EN = 0) else (x"0007" & x"C000" & S2_CLKOUT5(31 downto 30) & S2_CLKOUT0_FRAC_CALC(35 downto 32) & S2_CLKOUT5(25 downto 16));
rom(35) <= S1_CLKOUT0_FRAC_I;
-- Store CLKOUT6 divide and phase
rom(36) <= "0010010" & x"1000" & S2_CLKOUT6(15 downto 0);
S1_CLKOUT0_FRAC_J <= "0010011" & x"C000" & S2_CLKOUT6(31 downto 16) when (S2_CLKFBOUT_FRAC_EN = 0) else "0010011" & x"C000" & S2_CLKOUT6(31 downto 30) & S2_CLKFBOUT_FRAC_CALC(35 downto 32) & S2_CLKOUT6(25 downto 16);
rom(37) <= S1_CLKOUT0_FRAC_J;
-- Store the input divider
rom(38) <= "0010110" & x"C000" & ("00" & S2_DIVCLK(23 downto 22) & S2_DIVCLK(11 downto 0));
-- Store the feedback divide and phase
S1_CLKOUT0_FRAC_K <= "0010100" & x"1000" & S2_CLKFBOUT(15 downto 0) when (S2_CLKFBOUT_FRAC_EN = 0) else "0010100" & x"1000" & S2_CLKFBOUT_FRAC_CALC(15 downto 0);
rom(39) <= S1_CLKOUT0_FRAC_K;
S1_CLKOUT0_FRAC_L <= "0010101" & x"8000" & S2_CLKFBOUT(31 downto 16) when (S2_CLKFBOUT_FRAC_EN = 0) else "0010101" & x"8000" & S2_CLKFBOUT_FRAC_CALC(31 downto 16);
rom(40) <= S1_CLKOUT0_FRAC_L;
-- Store the lock settings
rom(41) <= "0011000" & x"FC00" & ("000000" & S2_LOCK(29 downto 20));
rom(42) <= "0011001" & x"8000" & ('0' & S2_LOCK(34 downto 30) & S2_LOCK(9 downto 0));
rom(43) <= "0011010" & x"8000" & ('0' & S2_LOCK(39 downto 35) & S2_LOCK(19 downto 10));
-- Store the filter settings
rom(44) <= "1001110" & x"66FF" & S2_DIGITAL_FILT(9) & "00" & S2_DIGITAL_FILT(8 downto 7) & "00" & S2_DIGITAL_FILT(6) & x"00" ;
rom(45) <= "1001111" & x"666F" & S2_DIGITAL_FILT(5) & "00" & S2_DIGITAL_FILT(4 downto 3) & "00" & S2_DIGITAL_FILT(2 downto 1) & "00" & S2_DIGITAL_FILT(0) & x"0";
-- Initialize the rest of the ROM
rom(46) <= "0101000" & x"00000000";
fill : for ii in 47 to 63 loop
rom(ii) <= "000000000000000000000000000000000000000";
end loop fill;
end process;
```