What is the use of Data strobe

[vijayanand_ME]

Dear All,
Please explain me what is the use of Data strobe in DDRAM. Already there is a read and write signal is there for transfering data right? Then what for Data strobe?

Thanks and regards,
Vijay

 

[mowgli]

Read and Write signals identify the type of access to the device performed by the user, the strobe signal validates the data on the bus.

Regards
Mowgli

 

[vijayanand_ME]

Helllo Mowgli,
Thank u for ur reply.. We have dedicated lines for address and data.. Then why we need to validate the data on the data bus?

 

[mowgli]

Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a suitable time after the start of data lines transitions to tell the reader that the data is valid in the sense that the transitions between logic levels on the lines have been completed.

Regards
Mowgli

 

[Slayerza]

It can be seen as a signal indicating that the applied voltages on the data / address lines are valid.

Cheers,
Slayer

 

[mmitchell]

Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a suitable time after the start of data lines transitions to tell the reader that the data is valid in the sense that the transitions between logic levels on the lines have been completed.

Regards
Mowgli

It can be seen as a signal indicating that the applied voltages on the data / address lines are valid.

Cheers,
Slayer

Then is this "strobe" is essentially just "data valid clock"? Why it doesn't just use the plain name "clock" or "CLK", or "DATA/ADDRESS CLK", but rather the pretty fancy "strobe" name that is more common in photography than in digital logic?


Matt

 

[rjkrocks]

Then is this "strobe" is essentially just "data valid clock"? Why it doesn't just use the plain name "clock" or "CLK", or "DATA/ADDRESS CLK", but rather the pretty fancy "strobe" name that is more common in photography than in digital logic?

Matt

Strobe means Sense ( Stroboscope is a instrument used for sensing)........

When we use the word strobe, we are telling the circuit that the the data (address) is ready and Sense it. (or since these device is not having any intellectual property, by the state in Strobe only they can have some 'sense' of valid values. If there is no sense it will be Non-Sense. That is why that particular pin is called STROBE.)

 

[mmitchell]

Strobe means Sense ( Stroboscope is a instrument used for sensing)........

When we use the word strobe, we are telling the circuit that the the data (address) is ready and Sense it. (or since these device is not having any intellectual property, by the state in Strobe only they can have some 'sense' of valid values. If there is no sense it will be Non-Sense. That is why that particular pin is called STROBE.)

What do you by "intellectual property"? Do you actually mean "intelligence"?

A basic flip-flop latches data/address at the rising edge of the clock signal, and this is the basic of synchronous digital logic. If DDR requires some special design such that data/address can be latched at both the rising and falling edge, I am sure there are good designs to implement them. But any way, even with double-edged latching mechanism the clock is still "clock", why comes the term "strobe", like a figure of speech?


Matt

 

[rjkrocks]

What do you by "intellectual property"? Do you actually mean "intelligence"?

A basic flip-flop latches data/address at the rising edge of the clock signal, and this is the basic of synchronous digital logic. If DDR requires some special design such that data/address can be latched at both the rising and falling edge, I am sure there are good designs to implement them. But any way, even with double-edged latching mechanism the clock is still "clock", why comes the term "strobe", like a figure of speech?


Matt

Originally posted by Mowgli
Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a suitable time after the start of data lines transitions to tell the reader that the data is valid in the sense that the transitions between logic levels on the lines have been completed.

so matt,

consider there are 4 flip-flops in total, let the required output is 1100........... The current state is 1010...... so in the next cycle we have to get the required output...Ok
and look the first flipflop state is no change 1
second flip flop change from 0 to 1
third flipflop change from 0 to 1
4th flipflop no change from 0
--------------------------------------------------------------
now in TTL design range from 0 volts to 0.5 volts for a "low" logic state, and 2.7 volts to 5 volts for a "high" logic state.

soin the next clock cycle suppose the transition mentioned is happening. it takes time. So if there is no mechanism to know weather this transition is completed, instead of a 1 in the IInd flipflop we may get a 0 (if transition is not completed). But by means of STROBE we can tell the system that the transition is completed and valid data is there. If there is not this mechanism as I said earlier, the data

will be Non-Sense

now,

What do you by "intellectual property"? Do you actually mean "intelligence"?

yes it is.............. we humans have the inteligence.........

Hope this clears your doubt. if not ask feel free to post.


-------------------------------

Note: in DDR the flipflops are not using, but the capacitors are used..
Iam not sure in DDR ttl is used but this is the basic principle

 

[FvM]

The original post is asking for the technical purpose of data strobe (DQS) signal of DDR RAMs. This is a reasonable question and can be answered. You're changing it into a matter of suitable definitions of technical terms or language criticism "shouldn't it be named clock?". Even if you have convincing arguments with you, this will lead to nothing, because the DDR RAM standard is in use since ten years or so and surely nobody would wan't to change etablished terms.

Nevertheless, terms like address strobe have been commonly used with multiplexed busses since much longer time, and thus most engineers will understand DQS in a similar way. As a special point with DQS signal, it's in fact an edge sensitive signal and in so far can be imagined as a kind of derived clock. But it's also a gated clock, not continuously toggling like DDR primary clock CK. And it's bidirectional.

 

[mmitchell]

As a special point with DQS signal, it's in fact an edge sensitive signal and in so far can be imagined as a kind of derived clock. But it's also a gated clock, not continuously toggling like DDR primary clock CK. And it's bidirectional.

RJK and FvM,

I noted that CLK signal (usually a differential pair) is an output from CPU's DDR2 controller and input to DDR2. It is an ungated continuously toggling clock as FvM described; Address and data strobes are derived from CLK, and in particular, data strobes can be bidirectional. It is mostly derived from CLK by gating, not quite likely by PLL operation.

Anyway, I believe this question is solved. Thanks very much.


Matt