Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what is the use of attribute

Status
Not open for further replies.

grittinjames

Advanced Member level 1
Joined
Jun 1, 2006
Messages
483
Helped
44
Reputation
90
Reaction score
32
Trophy points
1,308
Location
bangalore india
Activity points
3,985
pin_assign xilinx

hai
im very new to vhdl, while checking an example program i had seen this attribute

some one plz explai this


attribute pin_assign : string;
attribute pin_assign of clk : signal is "A7";
attribute pin_assign of left : signal is "G7";
attribute pin_assign of right : signal is "B2";
attribute pin_assign of stop : signal is "F2";
attribute pin_assign of q : signal is "G5 F6 C6 B4";
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
637
Reputation
1,272
Reaction score
88
Trophy points
1,328
Location
USA
Activity points
33,178
attribute pin_assign of clk : signal is a7;

Those attributes assign package pin numbers to various signals.

Some VHDL compilers don't try to interpret attributes. They simply pass them to the next step, such as place-and-route.

If you use a different synthesis tool, you may need to modify the attributes according to your tool's requirements. For example, Xilinx ISE expects "LOC" instead of "pin_assign".

Your synthesis tool may have a totally different way of specifying pin numbers, instead of using HDL attributes.
 

    grittinjames

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top