What is the significance of the different kind of PLL jitter

[albred]

There are four kinds of PLL jitter:
1.period jitter
2.short term jitter
3.long term jitter
4.cycle-to-cycle jitter
What is the significance of the different kinds of PLL jitters?

Now I think the "period jitter" can be considered as one part of "clock uncertainty" for STA normal "setup check" (one cycle path, not multi-cycle path), because the check is concerned about the clock edge to the next clock edge (flip-flop based path), and the "period jitter" can not affect the normal "hold check" which is concerned about the edges of the same clock cycle.
The "short term jitter" may be should be considered for muti-cycle path.
Is there any problem with my opinion?
Then what about "long term jitter" and "cycle-to-cycle jitter"?

Below are the definitions of these jitters:
Period Jitter (A), (JEDEC Definition - JESD65)
The edge deviation to the ideal FOUT when measuring the rising edge of FOUT after
(n+N)-th cycle by using the rising edge of FOUT at n-th cycle as the trigger point, where N=1. FOUT is PLL's output.
For short term jitter (B), N<10
For long term jitter ©, N must be large enough (ex, thousands)
(As show in figure 1)
Cycle-to-Cycle Jitter (JEDEC Definition - JESD65)
The cycle time variation between adjacent cycles over a random sample of adjacent clock cycle pairs.
(As show in figure 2)

 

[albred]

Re: What is the significance of the different kind of PLL ji

Can anybody help me.
It's important for our design.
Thanks