Basically I am writing a function that shall take a std_logic_vector of any length and return a string representing its hexadecimal equivalent. Therefore, I have created a hierarchy of functions where one calls the other to achieve this task. The idea is to divide the task into smaller tasks and these functions representing the smaller tasks can be used on their own as well. It has provided me with a way to practice certain aspects of my VHDL skills.
Now the specific function that this question is related to, takes a std_logic_vector upto 4 bits long and returns the single character hexadecimal translation of it. I want this function to be able to take 1 to 4 bit std_logic_vectors. However, if a longer std_logic_vector is passed to it, it must generate an error message which is why I have this assert statement.
The main function get_hex_string_from_slv, calls get_hex_char_from_slv being discussed here multiple times and fills in a string variable which is then returned at the end.