Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
lower metals are kept for nets connection that are not conducting heavy current.
top metals are for carrying heavy currents like clock,vdd,vss etc...
if we have wider metals in lower levels , you will face issues due to heavy capacitve effects of wide metals and biggest issue will be routing and die area.
e.g.
for a small inverter output having average current of 10uA , if u put a big metal your rise time fall time ,delays will not improve :
1. resistance will decrease due to increased width of metal
2. capacitance of that metal wire will also increase cap = (E * Area / D )
so overall your rc time contant will not decrease
but increasing metals width will increasr area of inverter due to more routing area required and overall your die size will increase ( cost increase )
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
