Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
TIA-644 is an industry spec that people can
agree on. As was not the case for other high
speed physical formats like CML. LVPECL et al
are other controlled-impedance "standards"
but less well defined re levels.
A matched transmission line should be free
of the overshoots, staircasing, intersymbol
interference that a straight wire (which is
still a transmission line, just one you know
about a priori) would produce and which
limit how fast you can throw data.
A low signal swing, for the same achievable
dV/dt, will have a higher data rate at the cost
of lower noise margin (this, determined by
amplitude vs the noise floor and line mismatch
effects). As an example I have seen a 400mV
LVDS driver hang tough out to >400MHz while
on the same die, an 8mA CMOS pad buffer at
80MHz failed to make full swing into the 50pF
nominal test load.
Sure, I understand that, could you tell me where exactly it would fit in the SERDES system in the below diagram. I am not able to connect the two; SERDES and LVDS.
From: Design of Integrated Circuits for Optical Communications By Behzad Razavi
"Input Data" and "Output Data", LVDS is a wired concept, it doesn't apply to optical links but it might apply to the signal path entering and leaving the diagram.
Sure, I understand that, could you tell me where exactly it would fit in the SERDES system in the below diagram. I am not able to connect the two; SERDES and LVDS.
View attachment 167457
From: Design of Integrated Circuits for Optical Communications By Behzad Razavi
In between the "Retimer" and "Laser Driver", if
separate packages / dice, would be a good
application (you want high serial BW there,
that interface appears not to have any
parallel "stuff" on either side of it).
Similarly between the TIA/Limiter block and
Decision Circuit (again, if these are disjoint
physical objects).
If this is all on-chip then you might elect to
use a CML or similar, low swing high speed
but non-transmission-line format, as the
loading and length are not needing a true
tline (until some GHz anyway).
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
