Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

what is the Pipeline architecture?

Status
Not open for further replies.

naresh850

Full Member level 3
Joined
Jun 9, 2006
Messages
157
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,298
Activity points
2,249
HI

could any one give me the brif discription about

what is the Pipeline architecture?

Regards,
NP
 

mowgli

Full Member level 2
Joined
Apr 5, 2002
Messages
149
Helped
34
Reputation
68
Reaction score
11
Trophy points
1,298
Activity points
1,348
The pipeline is a technique used to design the architecture of microprocessors.
Briefly: processing of information data often consists of performing a succession of different operations on input data. Therefore to optimize their performances, microprocessor cores are designed as blocks of cascaded elementary functional units, each one fed by the output of the previous unit: at every cpu clock the unit N process data outptut of unit N-1. The main reason for this choice is that simple processing blocks are able to run faster than complex ones, so pipelined structures allow the design of digital circuits working at GHz clock frequencies, with the throughput performances of nowadays modern processors.
This is (more or less) what is called pipelined architecture.
Due to this HW structure you will find the term pipeline also referred to SW, in the sense that the compiler translates SW instructions in the best way to fill the processor pipeline, decomposing the execution of complex instruction in a succession of elementary operations performed by the HW pipelines stages.
Hope that my explanation was helpful for you.
 

sohiltri

Member level 5
Joined
Dec 16, 2006
Messages
81
Helped
6
Reputation
12
Reaction score
1
Trophy points
1,288
Activity points
1,750
Perfect explanation....but u missed 1 point......
In pipeline arch not only u speed up clock but also overall time taken to process millions of instruction....
it is like this....in simple arch without pipeline....next input will have to wait until the current processin is completed....where as in pipeleine whole process is divided into minor process thus reducin critical path and next input can start processin after the current input has been processed by firs stage...thus N inputs are processed at same time parallely (u can say like tht) in N pipeleine stage but on each diff stage of computation is performed.....
 

avimit

Banned
Joined
Nov 16, 2005
Messages
413
Helped
91
Reputation
182
Reaction score
23
Trophy points
1,298
Location
Fleet, UK
Activity points
0
Actually pipelining is just not limited to Microprocessor cores. In digitial design it is exploited as much as possible:
To cut long timing paths, so that your design may work on higher frequencies, although the o/p latency would increase, but in most of the cases o/p latency can be eaisly compromised.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top