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The pipeline is a technique used to design the architecture of microprocessors.
Briefly: processing of information data often consists of performing a succession of different operations on input data. Therefore to optimize their performances, microprocessor cores are designed as blocks of cascaded elementary functional units, each one fed by the output of the previous unit: at every cpu clock the unit N process data outptut of unit N-1. The main reason for this choice is that simple processing blocks are able to run faster than complex ones, so pipelined structures allow the design of digital circuits working at GHz clock frequencies, with the throughput performances of nowadays modern processors.
This is (more or less) what is called pipelined architecture.
Due to this HW structure you will find the term pipeline also referred to SW, in the sense that the compiler translates SW instructions in the best way to fill the processor pipeline, decomposing the execution of complex instruction in a succession of elementary operations performed by the HW pipelines stages.
Hope that my explanation was helpful for you.
Perfect explanation....but u missed 1 point......
In pipeline arch not only u speed up clock but also overall time taken to process millions of instruction....
it is like this....in simple arch without pipeline....next input will have to wait until the current processin is completed....where as in pipeleine whole process is divided into minor process thus reducin critical path and next input can start processin after the current input has been processed by firs stage...thus N inputs are processed at same time parallely (u can say like tht) in N pipeleine stage but on each diff stage of computation is performed.....
Actually pipelining is just not limited to Microprocessor cores. In digitial design it is exploited as much as possible:
To cut long timing paths, so that your design may work on higher frequencies, although the o/p latency would increase, but in most of the cases o/p latency can be eaisly compromised.