What is the operating speed of Spartan 6 speed grade -3 ?

[ali8]

Hello,

I understand that Xilinx FPGAs comes in different speed grade. I am considering Spartan 6 speed grade 3.

How can I know what Mhz does this -3 corresponds to?

I have read the DC and Switching Characteristics (https://www.xilinx.com/support/documentation/data_sheets/ds162.pdf) but not able to find out.

For example, the DSP48A1 has a switching speed of 390 MHz. But what about the slices themselves?

If I am implementing some logic circuit, what is the speed that I can operate it on? I know this has also to do with the speed of the RAM, I/O, etc, but I mean like in a PC, we have specific speed for the CPU (e.g. 2 GHz).

 

[mrflibble]

And in that specificly specced 2 GHz cpu in that PC you have all sorts of seperate blocks and pipelines running at different speeds as well. Easiest example being memory controllers. So much for that analogy.

Just like the cpu, with the fpga there is no THE speed. You can run different parts at different speeds if the design requires it. Those switching speeds in the datasheet you just read is basically how fast they could make it with current process tech, and have fun building something with it. The fabric flip-flops will have a toggle rate about 1 GHz, block ram will be able to do 300+ Mhz or something, clock input buffer can take max <fill_in> MHz (little under 400 MHz I recall) and the PLLs can generate a wide range of frequencies. Sooooooo, no THE speed. Exactly like in a modern CPU with all sorts of different functional blocks.

 

[ali8]

I definitely understand that in a PC different components has different speeds, the slowest one being the bottle neck for the system as a whole.

But even then, you HAVE a "nominal" speed for the CPU, e.g. my Intel i3 runs @ 2.27 GHz.

What is the equivalent speed for the CLB - Configurable Logic Blocks ?

 

[mrflibble]

Guess despite you definitely understanding things about the different components inside a PC, you didn't entirely get my point about the cpu itself having several functional blocks inside that 1 single chippie that run at different speeds. Did I mention PC components? Nope. Did I mention just the cpu? Yup.

There is no "the equivalent speed". But perhaps you need a number to increase your happiness? Okay, spartan-6, about 300 MHz ballpark. There we go. Not that this number is going to help you anything, but there you have it.

- - - Updated - - -

Also, just ask on the xilinx forum and I suspect you'll get roughly the same answer.

 

[TrickyDicky]

The 300MHz figure is the maximum possible with the chip with a theoretically optimal design. So in reality you will struggle to get near that. It all depends on your design.

 

[FvM]

To discuss the relevance of different FPGA speed numbers, it's probably helpful to consider a real design problem. E.g. a kind of signal processing like a digital filter. The achievable data rate is usually the most interesting figure, in addition trade-off against number of pipelining levels and resource consumption.

You'll often find some performance data referring to basic signal processing structures, they are more informative than naked speed numbers for individual function blocks (e.g. DSP slices).

 

[mrflibble]

No no, you are forgeting about his requirement for a "specific speed". MUST HAVE NUMBER! @_@

But yes, you are quite correct that it's rather pointless as a performance metric. Almost as pointless as pure clock numbers to compare cpu performance (as if architecture doesn't matter), so in that regard I kind of like the symmetry.

As for 300 MHz being a struggle on spartan-6 ... nah. 400 MHz is struggling (and accidentally overclocking global clock nets a tiny bit). 300 MHz is just hard work and making sure you don't go over 2 logic levels. Well okay, getting data in and out of bram's from a relatively large area at full rates is annoying even at 300 MHz. Costs you a few extra FF stages to get everything routed and still meet timings. This being at the expense of some extra pipeline stages. So I wouldn't quite say it requires a theoretically optimal design, but it's not totally trivial either.

And as pointed out, the number doesn't mean squat without proper context. I could just as well have written 780 MHz, which is perfectly valid. 390 MHz clock, and just do some boring toggling on DDR flip-flops. Those CLBs have no problem with that, and neither do the FFs. You'll have a hard time doing anything meaningful with easy to read HDL at that speed, but what the hell, we have a number.

 

[ali8]

Thanks everyone for the answers.

The point is that I didn't just "want a number" for the sake of a number, I just wanted some rough estimate to know around what value we are doing work.

Thanks again.