Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In the case of TSMC process, PSUB2 is a dummy layer. It is used when you have multiple power (for example analog and digital) and you are not using deep nwell.
More concretly, let's say you have agnd and dgnd. When fabricating the chip the substrate is common so there is a connection.
You will have 2 diffrents ground pins, but they are connected so when doing the LVS it will generate an error.
Using a PSUB2 region for the digital (for example) the two region are not connected during the LVS thus making the use of 2 pins possible.
Hope it's not to confuse
when u have multiple grounds in ur design,while running the LVS u need to seperate the grounds using the psub2 layer. ie if u have 2 grounds say gnda and gndd u need to cover either the gnda or gndd using the psub2 layer. also this ajust an LVS layer not a mask or derived layer. but u should be very careful while using this layer.