What is the minimum capacitance with good mismatch?

[rockycheng]

Hi,

In my design, several sampling capacitors are used in a high accuracy SAR-ADC. τ should be kept very small to meet the requirement. That means that both R and C should be quite small. The calculation shows that the smallest C is around 100fF. Is this possible to be implemented in layout with good accuracy? And what about the resistance?
Thanks a lot.

Regards,
Rocky [/b]

 

[arno_a_boy]

less capacitance needs smaller area on the cheap.
100ff is possible and a good size for integration.
for resistors better to have resistors less than 100k
the smallest res. as i know is 10 ohms.

 

[snoop835]

Hi RockyCheng,

Can you tell me how you go about designing the front end circuit of your SAR (Sample-hold/DAC). If I use Charge Redistribution method for my SAR, how do I decide the capacitance value and what is the optimum value for minimum mismatch.

Thanks

 

[Vamsi Mocherla]

One good way of getting a better layout value is to put 2 caps in series and 2 in parallel for getting more accurate layouts. For example, if you have to realize a 100 fF cap, which is the most basic value, you can put two 100 fF caps in series to get an effective cap of 50 fF and then parallel them with a similar configuration. So, effectively you get 100fF.

The drawbacks for this is more area. Hence this technique can be used for smaller values of caps. The same can be done for the resistors. If you want to realize a 10 Ohm resistor, lay 10 resistors of 100 ohm each in parallel.

If you are laying out bigger values, there is no need for this technique......

 

[rockycheng]

Thank you! I'll try this layout method.

 

[ravig]

Hi,
As Vamsi said you need to realise small values of resistors or capacitors by layout multiple fingers of large values( using series and parallel combinations). This averages the mismatch errors.
Current technologies are capable of achieving +/-0.1% mismatch in capacitors. Check the mismatch parameters provided by your foundry. And you have to check if this mismatch is ok for you. If that mismatch is not ok for you, then you have to think of the trimming options or adding a calibration circuit to your ADC. As far as I know 0.1% mismatch is ok for resolutions of 8-10 bits(atleast in pipelined ADCs). I don't know much about SAR ADC.

I hope this helps

ravi