What is the meaning of this VHDL line?

[testing test]

Hi,

What is the meaning of this VHDL line?

ADC_x <= (ADC_r(RESOLUTION-2 downto 0) & sdto) when (phase = SCLK_RISING_EDGE) and (bit_cnt < RESOLUTION) else ADC_r;

Thank you.

 

[alexan_e]

Suppose for example that RESOLUTION is 8 and sdto is 1

ADC_r(RESOLUTION-2 downto 0) & sdto) translates to ADC_r(8-2 downto 0) & '1') which is the 7 bit ADC_R (for example "1010100" concatenated with '1' , result is "10101001"

ADC_x <= (ADC_r(RESOLUTION-2 downto 0) & sdto) when (phase = SCLK_RISING_EDGE) and (bit_cnt < RESOLUTION) else ADC_r;

so ADC_x will be assigned the value of ADC_R concatenated with stdo when (phase = SCLK_RISING_EDGE) and (bit_cnt < RESOLUTION) is true or else it will be assigned the value of ADC_r.

Alex