What is the meaning and effect of Design Flattening?

[vlsi_freak]

Hi,

What is the meaning of Design Flattening.

Will i get any change in timing when flattening is done in a design ?

Please share your thoughts,

regards,
freak

 

[cafukarfoo]

Re: Design Flattening

Design flatten mean reduce the logic level between input and output.

Design flatten will make the design area bigger.

For example:
Y = ABC + BCD ( 1 logic level ) - design had been flatten in this case

or


Y = BC (A + D) ( 2 logic level )

Hope this help. THanks.

 

[hiral.kotak]

Re: Design Flattening

Hi,

Design flattening means you are collapsing the hierarchy levels, there will be only one top module in the design after flattening all the subblocks are treated as gluelogic of the main top module, while in the unflattened there will be more than one design modules having their individual glue logic.

It may help you.

Thanks..

HAK..

 

[viju]

Design Flattening

Hello hiral.kotak,
Design flattening means what "cafukarfoo" said.
What ever you mentioned is hierarchy fattening.
Both are different thigs. Don't confuse between these two.

 

[vlsi_freak]

Re: Design Flattening

Hi Cafukarfoo,

Thanks for you reply.

You had mentioned that, design flattening reduces area, but from your example levels of logic got increased.

Is there any advantage for a designer by flattening a design. When exactly a designre goes for flattening - when timings are not met or when area is not met.

Regards,'
freak

 

[viju]

Design Flattening

Hi vlsi_freak,
This can happen, that while doing the design flattening ... it may increase your area...
Generally we go for it while we have to meet the timings... but agianst that we have to pay in terms of area some times...

Synthesis gurus... Please correct me if i am missing any thing !

 

[pmat]

Re: Design Flattening

What you are trying to describe, is called collapsing in terms of Logic Synthesis, i.e. a multilevel Boolean Network is collapsed to a two level Boolean Network(PLA actually). Of course this yields a great area overhead, as common subparts of Boolean expressions(kernels co-kernels etc.) are not used to minimize the Boolean Equations. Moreover the fanouts of the first logic level gates to the second are quite huge and thus timing is also a problem here...

Cheers,
Pavlos

 

[alexan56]

Design Flattening

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[VLSI_guru22]

"cafukarfoo" and "viju" are both completely wrong.

Design flattening merges modules from different levels in the design hierarchy. In effect, it shrinks the design hierarchy to make it easier for design automation tools to optimize the design.

Don't take my word for it. Check out the documentation from the Xilinx corp....