First off I assume you mean low frequencies or @ DC. Things can change drastically at high frequencies.
Secondly you should go to your 130nm Design Manual and look up what types of passives are allowed for your process. (MiM, VNcaps, NFETcaps; just to name a few types of capacitors). The design manual will give you equations for how to calculate the value of your passive element as a function of area.
Next figure out how much area you can waste on passive elements. If you want to take make your whole chip into a giant inductor go for it. Ask Intel to make you a 45nm, 12 inch wafer cap!!
Thus we can't tell you what the max sizes are, its all about trades offs.
Here are some rules of thumb:
1nF is really large for caps
10kohms or less for resistors
10nH for inductors
Next thing to consider is that just about any passive can be faked (crappy faked) with transistor. Long channel length transistors for Mega-ohms resistors, inductor being replaced with transistors in tank oscillators, and lots more tricks.
Cheers,
Hemlock