what is the issue with this code? Need help in synthesis

[verilog2vhdl]

I see the following errors ... pls help me in solving this...

# Error: [46839]: "C:decoder3x8.vhd", line 30: Non-static range. Continuing ...
# Error: [46292]: Module work.decoder3x8(translated) cannot be compiled because it contains non-rtl constructs. Please check the log for warnings or errors about non-synthesizable constructs in this module.

Thanks

 

[alieeldin]

1- dont use bit_vector since you will make a calculation
2- in 30 line you wrote to get the length of val and you didnt desided the length of it.
3- try to write it by RTL it is better.