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what is the importance of S22 in an LNA??

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bcdeepak

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plz help me

i designed a inductively degenerated cascode LNA. its noise fig, S11,S21 are fine
but its S22 is too poor , around 0.35db

i tried a lot to change it , but it is not at all changing and the changes are affecting the other parameters.


is this value of S22 is allowable in LNA??
 

I think you should ask the RF system Engineer in your team for the correct answer
 

    bcdeepak

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This value of S22 is unacceptable. You may simulate or measure output impedance of your LNA as Z22=R22+jX22 and plot these parameters. It will help you to see where the output resistance and reactance of your LNA are and what you should do to shift them to desired direction. This is fast and proven way to fix such problem.
 

    bcdeepak

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If S22 is very poor that means , output impedance of your LNA is far away from 50 Ohm and this can be requested case sometime.Therefore, if you have a poor S22, you should check impedance zone( capacitive or inductive) to match to the next stage..

It's not very possible that "if S22 is very poor, LNA is bad designed.."..sometime it's wanted case..
 

You can try following 2 thing.
1) change the common terminal of transistor & redesign for the same.
( suppose you are using common source then try for common base)
or
2) Add inductive or capacitive element in common terminal which will change your s11 & s22.

I hope this will work
Abhishekabs
 

Something wrong. Better than -15dB is typical RL for an LNA. What's the device size u are using?
 

may be you should check your design procedure,
Try some photonic crystals at the output, maybe they can change the output impedance.
 

thank you very much for ur replies

i am using 0.18um technology .

i used a 15 ohm resistor in series with the output , and resimulated,so now s22 is improved to 10.9db.

and because of this resistor my s21 became less , s21 value is 7.8db,

can use this way???

s21 =7.8db is agreeable ??
 

i think it will depend on ur spec's , of the LNA , i think u need to make the LNA have more gain "S21" ,

don't forget that the resistor will change th DC bias point , of the transistors so u need to adjust the bias point

khouly
 

It depends on how you define the impedance of your port#2.
 

u can increease the gm of the transsitor , by the dimesions or by chnging the current , also check the matching , ad so on , increasign the load

khouly
 

You can improve S21 by adding feedback in circuit.
 

feedback will decrease the gain , so it will decrease the S21

khouly
 

Check the MAXIM, AnalogDevice or any chip manufacturer's LNA to see the specs, especially those who have same applications with your design. Make a comparison and you'll see whether your results are acceptable or not.
 

thank you very much for ur replies

i am using 0.18um technology .

i used a 15 ohm resistor in series with the output , and resimulated,so now s22 is improved to 10.9db.

and because of this resistor my s21 became less , s21 value is 7.8db,

can use this way???

s21 =7.8db is agreeable ??

The easiest way to improve S22 is to include an attenuator at the output. It will improve S22 by twice of the attenuation of the pad while reduce the gain only proportional to attenuation. This is quick and dirty solution, but it may help.

Actual gain must meet spec as well as all other parameters.

Best regards,
RF-OM
 

Well if you cannt add attenuator at output port because of gain specs and P1dB specs (if any), then maybe some stub matching can be tried in the assembly... (once fabricated of course)...otherwise, in design stage, you need to try different matching techniques... also you may try twiging your bias chokes and source bypass capacitors...
 

Of course improtant, because it will impact you total gain.
 

S22 being less can be acceptable.
check what is the input impedance of the next stage!

s21 should be high, generally it vil be 10dB (again it depends on ur spec) in one of the designs i saw, it was 20dB!

if you put bigger resistance in series with the inductive load, the noise will increase!!

please check with the next block designer, what is his input impedance and match the LNA output impedance with input impedance of the next stage.
 

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