phoenix_pavan
Banned
Why would a testbench not have pins (port) on it?
When declaring a flip flop, why would not you declare its output value in the port statement?
Is Verilog (or that matter any HDL) is a concurrent or sequential language?
What is the function of sensitivity list?
When declaring a flip flop, why would not you declare its output value in the port statement?
Is Verilog (or that matter any HDL) is a concurrent or sequential language?
What is the function of sensitivity list?
