Aug 2, 2008 #1 D dolby.yang Member level 4 Joined Mar 2, 2005 Messages 73 Helped 10 Reputation 20 Reaction score 2 Trophy points 1,288 Activity points 1,862 what is the FPGA I/O status before configuration after power up? Tks!
Aug 2, 2008 #2 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,413 Helped 14,749 Reputation 29,780 Reaction score 14,097 Trophy points 1,393 Location Bochum, Germany Activity points 298,068 Many FPGA have unconditionally active weak pull-up resistors, some provide a selection between high impedance and weak pull-up by pin-strapping.
Many FPGA have unconditionally active weak pull-up resistors, some provide a selection between high impedance and weak pull-up by pin-strapping.
Aug 4, 2008 #3 D dolby.yang Member level 4 Joined Mar 2, 2005 Messages 73 Helped 10 Reputation 20 Reaction score 2 Trophy points 1,288 Activity points 1,862 Thx. i got it !