what is the effect to chip if latency is high!

[godsun]

high latency mean long delay ? then which will result in low frequency, isn't it?

 

[Mirzaaur]

latency is not necessary means to have lower frequecny. Depends on the architechture of design (pipe lined / paralell...etc) it can be conseidered as number of cycles used to have out put after and frequncy can be higher too.

what decide about lower or higher frequecny is maximum delay in a combinational path (critical path delay), in a pipelined architecture it is maximum possible delay within two stages.

hope its clear!

all the best,

 

[godsun]

thank, i know, but i have not understand that what is related to latency.
chip will have a slow reset?

 

[Guru59]

May be this Eg. helps you out.......

E.g.: 133 MHz CL3 Device (7.5 ns per cycle, 3 cycle request latency)
100 MHz CL2 Device (10 ns per cycle, 2 cycle request latency)

First Bit would be available after :
Case 1 : 22.5 ns (7.5 * 3)
Case 2 : 20 ns (10 * 2)

So, it can be stated as LOWER Latency BETTER Performance.

But,With a Burst Reading Capability of 6 bits.
Case 1 : 60 ns (7.5 * 3 latency + 7.5 * 5 after first)
Case 2 : 70 ns (10 * 2 latency + 10 * 5 after first)

So,it can be stated that HIGHER Clock Speed Wins.

 

[maverick_mind]

Latency is the amount of time lapsed between input applied and meaningful output received. It is not directly related to frequency. Latency is determined by the number of stages between input and output.

Frequency is determined by the critical path delay ie the delay of the longest path.

Infact if more pipeline stages are added to the design, its critical path can be reduced and thus its frequency can be increased but (generally) latency also increases.

 

[cdic]

thank, i know, but i have not understand that what is related to latency.
chip will have a slow reset?

Depends on your reset stratedgy and reset circuit.
Long latency won't slow down your chip speed, but it will slow down your chip interface timing in general.
If you move to 90/65nm, long clock latency is critical to your design, you need to make it as short as possible.
actually it's a quite interesting topic for 90/65nm design.

 

[caplash_vlsi]

latency means the time difference between your input arrival on input ports and that when output is received.......so this directly affects the max. freq at which your design will work.......

 

[Mirzaaur]

As others friends mentioned longer latency can be result of the pipelined stages. I just want to add my comment that "RESET" mechanism must be designed very carefully specially the "ASSERT" and "RELEASE" of reset with respect to active clock edge.

effects fo flawed "reset mechanism":-

some time internal invert logic of at any stage may cause functional verification to fail / error .

if your design is featured with any kind of internal error correction algorithm (for example hamming for state machines...) then the timing of interface will not be repeatable (different for different runs).

have a nice week end!

mirza