[SOLVED] What is the difference between VHDL attributes left, right and low, high?

[matrixofdynamism]

What is the difference between VHDL attributes left,right and low,high?

It seems to me that the behaviour of some VHDL attributes is overlapping which is making me confused reading about them.

(1) What is the difference between the atrribute pairs low,high vs right,left when used with scalar and when used with array type e.g std_logic_vector?


Also, for an array what is the difference between the following notations:

A'RIGHT is the rightmost subscript of array A or constrained array type.
A'RIGHT(N) is the rightmost subscript of dimension N of array A.

(2) I assumet that N would be used for multideminsional arrays. Is that correct?

 

[K-J]

Re: What is the difference between VHDL attributes left,right and low,high?

(1) What is the difference between the atrribute pairs low,high vs right,left when used with scalar and when used with array type e.g std_logic_vector?

Scalars don't have these attributes, only arrays.

Also, for an array what is the difference between the following notations:

A'RIGHT is the rightmost subscript of array A or constrained array type.
A'RIGHT(N) is the rightmost subscript of dimension N of array A.

For a multi-dimensional array, if you don't supply 'N', the default is to return the right most subscript of the first dimension of A.

(2) I assumet that N would be used for multideminsional arrays. Is that correct?

Correct.
Kevin Jennings

 

[TrickyDicky]

Re: What is the difference between VHDL attributes left,right and low,high?

Scalars don't have these attributes, only arrays.

All scalars support 'left, 'right, 'high and 'low.
integer'left and integer'low are legal (and are the same).

All scalars initialise to T'left.

 

[K-J]

Re: What is the difference between VHDL attributes left,right and low,high?

All scalars support 'left, 'right, 'high and 'low.
integer'left and integer'low are legal (and are the same).

All scalars initialise to T'left.

Good point, but integer is a type, not a scalar which I was considering (perhaps incorrectly) as being an object. Types do have 'left, 'right, etc. attributes but an object (i.e. a signal/variable) of a scalar type, such as integer, does not. I was thinking more along the lines of the signal/variable object itself, not the type.

Kevin Jennings

 

[matrixofdynamism]

Re: What is the difference between VHDL attributes left,right and low,high?

With signal slv: std_logic_vector(7 downto 0);

Pair slv'left & slv'right is same as slv'high & slv'low as 70 70

However, with signal slv: std_logic_vector(0 to 7);

Pair slv'left & slv'right is not same as slv'high & slv'low as 07 70

In the latter case the results are flipped.

I can see why this was confusing me now. VHDL has 2 ways to specify the array range using (a downto b) or (b to a)

Then there is also the possibility of specifiying array type like signal slv: std_logic_vector(15 downto 8)

 

[vGoodtimes]

Re: What is the difference between VHDL attributes left,right and low,high?

This is correct. VHDL's default is 0 to N-1 for std_logic_vector as well. This mostly is important when you have "unconstrained vectors" in functions or port maps.

keep in mind that this is just indexing. if you have x(0 to 3) and y(3 to 0), x <= y means x(0) <= y(3), x(1) <= y(2), x(2) <= y(1), x(3) <= y(0). There is no re-ordering of bits from left to right.

I typically use 'length or 'range. But 'high/'low/'left/'right can be useful in some cases.