What is the difference between two code?

[lupineye]

When I make the counter with DLL, I used the below two code, but when clock goes higher, the second code didn't work. Can anyone tell me why?
thank you

first ,

process (clk, rst)
begin
if rst ='1' then
counter <= (others => '0);
elsif clk'event and clk='1' then
counter <= counter +1;
end if;
end process;

second,

process (clk, rst)
begin
if rising_edge(clk) then
if rst ='1' then
counter <= (others =>'0');
else
counter <= counter +1;
end if;
end process;

 

[bansalr]

The second code is fundametally worng. Remove the rst from the senstivity list.

 

[ankit12345]

first code has asyncronous reset................
second has synchronous reset..................

what type of reset u need????

 

[Aastik]

Yes, as ankit said, first code has Asynchronous reset whereas the second one has Synchronous reset. Both the schemes are ok and both are supposed to work. When you say the second code didn't work, does it mean it didn't work in simulation or it didn't work on board?
Well, one small thing...... the reset pulse width should be more than the clock period for the second code.

Regards.

 

[shiv_emf]

well for synchronous design ! v need not bother about rst .. so v can remove it frm sensitivity list

 

[bis_]

add missing "end if" in second code

process (clk, rst)
begin
   if rising_edge(clk) then
      if rst ='1' then
         counter <= (others =>'0');
      else
         counter <= counter +1;
      end if;
   end if;  --<---- added line
end process;

and remember that it uses synchronous reset. it will be better if you keep "rst" in the sensitivity list.

bis

 

[keano]

The second code will only work if the rst is up on a rising edge of the clock.

Since it's a synchronous reset, it shouldn't be present in the sensibility list of the process.

 

[xuzaiwang]

if clock is higher, the second case will not be reset!

i.e. reset high pulse is shorter than clock period!

 

[shiv_emf]

if clock is higher, the second case will not be reset!

but y ??

 

[xuzaiwang]

i.e. reset high pulse is shorter than clock period!

when clock rising, reset may be low level, so the reg signal is in unknow state forever!